Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2003-03-21
2004-12-07
Smith, Matthew (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S741000, C257S734000, C257S712000, C257S782000
Reexamination Certificate
active
06828684
ABSTRACT:
This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2000-272211, filed Sep. 7, 2000; and No. 2001-218528, filed Jul. 18, 2001, the entire contents of both of which are incorporated herein by
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, particularly, to a semiconductor device including a copper wiring and a method of manufacturing the same.
2. Description of the Related Art
In the conventional semiconductor device, aluminum is widely used as the material of the wiring. In recent years, copper having a lower resistivity and cheaper has come to be used as a wiring material in place of aluminum. However, if a Cu wiring is subjected to a heat treatment in an atmosphere containing oxygen, oxidation of the Cu wiring surface proceeds, with the result that the resistance of the wiring is markedly increased.
FIGS. 1A
to
1
C are cross sectional views schematically showing a conventional process of forming a multilayer interconnection structure. As shown in
FIG. 1A
, a first interlayer insulation film
13
is formed on a semiconductor substrate
2
, and a first Cu wiring
14
is buried in the insulation film
13
. Incidentally, the Cu wiring
14
is the one which contains mainly Cu and has a layer or layers containing a material such as Ta, TaN, Ti or TiN on the sidewalls and bottom surface thereof.
In the conventional process, an interlayer insulation film
23
is formed as a continuous film on the insulation film
13
and the wiring layer
14
, followed by forming a resist pattern
5
on the insulation film
23
, as shown in FIG.
1
A. It is noted that interlayer insulation film has a single-layer or a multi-layer structure and includes a film such as a silicon nitride film (herein after referred to as “SiN film”), silicon oxide film, organosilicon film or organic insulation film. In the next step, a groove for a second Cu wiring is formed in the insulation film
23
by a reactive ion etching (hereinafter referred to as “RIE”) by using the resist pattern
5
as a mask, as shown in FIG.
1
B. Incidentally, the Cu wiring
14
is exposed to the outside for the via contact in a part of the bottom surface of the groove formed in the insulation film
23
. Then, the resist pattern
5
is removed by the ashing in an atmosphere containing oxygen. In this step, the uncovered portion of the Cu wiring
14
, which is exposed to oxygen at a high temperature, is oxidized so as to form an oxide film
14
a
made of, for example, Cu
2
O, as shown in FIG.
1
C. By the oxidation of Cu into Cu
2
O, the Cu
2
O layer is expanded to a volume 1.65 times as much as the original Cu layer. As a result, where the oxide film
14
a
is formed as shown in
FIG. 1C
, cracks tend to be generated around the oxide film
14
a.
A similar problem also takes place in the case where copper is used as a material of an electrode such as a bonding pad.
FIGS. 2A and 2B
are cross sectional views schematically showing a conventional bonding process. In
FIG. 2A
, an interlayer insulation film
13
is formed on the semiconductor substrate
2
, and a bonding pad
4
made of copper is buried in the insulation film
13
. Further, an SiN film
6
and an insulation film
23
are successively formed on the insulation film
13
.
The bonding of an Au wire to the pad
4
shown in
FIG. 2A
is carried out generally in the air atmosphere under the state that the substrate
2
is heated to a high temperature. Therefore, the surface of the pad
4
is exposed to a high temperature oxygen so as to be oxidized, resulting in formation of an oxide film
4
a
made of, for example, Cu
2
O. It follows that cracks are generated around the pad
4
so as to cause a peeling problem in some cases.
The process shown in
FIGS. 3A
to
3
F and the process shown in
FIGS. 4A
to
4
C are known to the art as the process for preventing the occurrence of the cracks described above with reference to
FIGS. 1A
to
1
C,
2
A and
2
B.
FIGS. 3A
to
3
F are cross sectional views schematically showing another conventional process of forming a multilayer interconnection structure. In the conventional process, a Cu wiring
14
is formed first as shown in
FIG. 3A
, followed by forming an SiN film
16
, an interlayer insulation film
23
and a resist pattern
5
, as shown in FIG.
3
B. Then, a groove is formed in the insulation film
23
by RIE with the resist pattern
5
used as a mask, as shown in FIG.
3
C. In this etching step, the SiN film
16
plays the role of an etching stopper. Then, the resist pattern
5
is removed by the ashing carried out in an atmosphere containing oxygen
11
, as shown in FIG.
3
D. In the next step, that portion of the SiN film
16
which is positioned within the groove is removed by etching as shown in
FIG. 3E
, followed by filling the groove with copper to form a Cu wiring
24
, as shown in FIG.
3
F. According to this process, the Cu wiring
14
is covered with the SiN film
16
and, thus, is not oxidized in the ashing step. It follows that it is possible to prevent the crack occurrence.
FIGS. 4A
to
4
C are cross sectional views schematically showing another conventional bonding process. In this process, the interlayer insulation film
13
, the bonding pad
4
made of copper, the SiN film
6
, and the insulation film
23
are formed successively on the semiconductor substrate
2
, as shown in FIG.
4
A. In the next step, an aluminum electrode
7
is formed to cover the side walls and the bottom surface of the groove formed in the SiN film
6
and the insulation film
23
, as shown in FIG.
4
B. Then, an Au wire
8
is bonded to the electrode
7
, as shown in FIG.
4
C. It should be noted that, in this process, the bonding pad
4
within the groove is covered with the aluminum electrode
7
, with the result that the bonding pad
4
is not oxidized in the bonding step of the Au wire
8
.
As described above, in the process shown in
FIGS. 1A
to
1
C and in the process shown in
FIGS. 2A and 2B
, the surfaces of the Cu wiring
14
and the Cu pad are oxidized. In contrast to the processes, it is possible to prevent the surfaces of the Cu wiring
14
and the Cu pad
4
from being oxidized in the processes described with reference to
FIGS. 3A
to
3
F and to
FIGS. 4A
to
4
C. On the other hand, however, required are additional step of forming the SiN film
16
, the etching step and the step of forming the Al electrode
7
.
It is possible for another problem to occur in accordance with oxidation of the Cu wiring and the Cu pad. For example, if a potential difference is generated between the Cu wiring and the interlayer insulation film, copper oxide tends to be ionized so as to be diffused into the insulation film. Such a diffusion brings about increases in the wiring resistance and in the wiring capacitance. In general, an SiN film or an SiCH film is formed as a diffusion barrier film by a chemical vapor deposition (hereinafter referred to as “CVD”) on the surface of the interlayer insulation film in which is buried the Cu wiring. What should be noted is that it is difficult for the bonding strength between the SiN film or the SiCH film and the copper oxide film to be maintained in a satisfactory state.
It is possible to suppress the problem accompanying the oxidation of the Cu wiring by applying a surface treatment to the Cu wire by utilizing a plasma using, for example, an NH
3
gas or an H
2
gas as the raw material. However, such a plasma processing gives rise to the problem described below.
In the conventional semiconductor device having a multilayer interconnection structure, a silicon oxide film having a relative dielectric constant &kgr; of about 4.1 was used in general as an interlayer insulation film. In recent years, vigorous studies are being made in an attempt to put into practical use a multi-layer interconnection structure in which an organosilicon film or an organic film having a relative dielectric constant &kgr; of about 4.1 is used as the interlayer
Hayasaka Nobuo
Hisatsune Yoshimi
Ikegami Hiroshi
Nakata Rempei
Yoda Takashi
Anya Igwe U.
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Smith Matthew
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