Active solid-state devices (e.g. – transistors – solid-state diode – Alignment marks
Reexamination Certificate
2002-11-06
2004-09-21
Clark, S. V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Alignment marks
Reexamination Certificate
active
06794763
ABSTRACT:
Japanese Patent Application No. 2001-355070 filed on Nov. 20, 2001, is hereby incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a measurement mark region and a method of manufacturing the same.
When manufacturing a semiconductor device, there is a case where a predetermined portion is measured during the manufacturing process. The measurement is generally performed by using electron beams. However, an irradiated area may react with the electron beams and cause problems in the subsequent processing.
BRIEF SUMMARY OF THE INVENTION
The present invention may provide a semiconductor device which enables the dimensions of a predetermined portion to be obtained without causing characteristics of the semiconductor device to be adversely affected, and a method of manufacturing the same.
A semiconductor device as one aspect of the present invention comprises:
an effective pattern region and at least one measurement mark region,
wherein the measurement mark region includes a measuring objective portion, and
wherein the measuring objective portion has the same shape as a portion forming part of the effective pattern region.
A first method of manufacturing a semiconductor device as another aspect of the present invention is a method of manufacturing a semiconductor device including an effective pattern region and at least one measurement mark region,
wherein the measurement mark region includes a measuring objective portion,
wherein the measuring objective portion has the same shape as a portion forming part of the effective pattern region,
wherein the method comprising:
forming a portion that constitutes part of the effective pattern region in the effective pattern region and forming the measuring objective portion having the same shape as the portion that constitutes part of the effective pattern region in the measurement mark region; and
measuring the measuring objective portion.
A second method of manufacturing a semiconductor device as a further aspect of the present invention is a method of manufacturing a semiconductor device including an effective pattern region and at least one measurement mark region,
wherein the measurement mark region includes a first portion which forms part of the effective pattern region, and a second portion which corresponds to the first portion,
wherein the method comprising:
forming a third portion necessary for forming the first portion in the effective pattern region and forming a fourth portion necessary for forming the second portion in the measurement mark region so that the third portion and the fourth portion have the same shape; and
measuring the fourth portion.
REFERENCES:
patent: 5892291 (1999-04-01), Narimatsu et al.
patent: 6114072 (2000-09-01), Narimatsu
patent: 6314543 (2001-11-01), Ymaguchi
patent: 63-291431 (1988-11-01), None
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patent: 05-119467 (1993-05-01), None
patent: 07-153667 (1995-06-01), None
patent: 07-297252 (1995-11-01), None
patent: 09-213901 (1997-08-01), None
patent: 10-056048 (1998-02-01), None
Clark S. V.
Hogan & Hartson LLP
Seiko Epson Corporation
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