Active solid-state devices (e.g. – transistors – solid-state diode – Thin active physical layer which is – Heterojunction
Reexamination Certificate
2003-04-23
2004-09-14
Jackson, Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Thin active physical layer which is
Heterojunction
C257S388000, C257S412000, C257S151000, C257S407000, C257S616000, C257S611000, C257S607000, C257S402000, C257S020000, C257S364000
Reexamination Certificate
active
06791106
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device including a metal-insulator-semiconductor filed effect transistor (MISFET) and a method of manufacturing the same.
2. Related Background Art
It is known that in a MISFET or MOSFET, a hot carrier is generated as a result of electric field concentration at a gate edge, thereby to degrade the reliability of gate breakdown voltage. In order to prevent this, side portions of the gate are oxidized to thicken an insulating layer at the gate edge obtained by oxidizing the gate side portion, i.e., a reoxidized layer, to moderate the electric field intensity near the gate edge. However, a sufficient thickness of the reoxidized layer is required to appropriately moderate electric field. If a reoxidized layer
12
with a sufficient thickness is formed as shown in
FIG. 8
, this oxidized layer
12
may hinder subsequently-performed very-low-acceleration ion implantation or impurity doping using plasma, using gate electrodes
8
a
and
8
b
as masks, for forming an n-type extension layer
16
and a p-type extension layer
17
having a lower impurity concentration than n-type source/drain regions
20
and p-type source/drain regions
21
. In
FIG. 8
, the reference numeral
1
denotes an n-type semiconductor substrate,
2
a
denotes a p-type semiconductor region,
2
b
denotes an n-type semiconductor region,
4
denotes a device isolating insulating layer, and
6
a
and
6
b
denote gate insulating layers.
Generally, polycrystalline silicon-germanium is used as a material of a gate electrode to activate an impurity (e.g., boron). When the reoxidized layer
12
with a sufficient thickness is formed as shown in
FIG. 8
, the edges of the gate electrodes
8
a
and
8
b
have a higher resistance value than the central portion
34
since deactivation of the impurity doped to make polycrystalline silicon-germanium conductive occurs at the side portions of the gate electrodes
8
a
and
8
b
. In a gate electrode which is particularly miniaturized, the proportion of the above-described deactivated portion in the gate electrode increases, thereby to form a depletion layer in the gate electrode. Accordingly, the capability of driving current of transistor is reduced, and the performance of MISFET is degraded.
Besides having a higher impurity activation ratio than polycrystalline silicon, which has conventionally been used as a material of gate electrode, polycrystalline silicon-germanium has a property that the band gap thereof is lower than that of polycrystalline silicon. In order to achieve a low threshold value with such a property, the substrate impurity concentration should be reduced as compare with the case where polycrystalline silicon is used. Generally, in order to inhibit the short-channel effect, the substrate impurity concentration should be set to be as high as possible. Accordingly, if polycrystalline silicon-germanium is used as the material of gate electrode, it is possible that the performance of the MISFET is degraded due to the short-channel effect. The above-described problem is especially noticeable in P-type MISFETs.
SUMMARY OF THE INVENTION
A semiconductor device according to a first aspect of the present invention includes: a first conductive type semiconductor region formed in a semiconductor substrate; a gate electrode formed on the first conductive type semiconductor region; a channel region formed immediately below the gate electrode in the first conductive type semiconductor region; and a second conductive type first diffusion layer constituting source/drain regions formed at opposite sides of the channel region in the first conductive type semiconductor region, the gate electrode being formed of polycrystalline silicon-germanium, in which a germanium concentration is continuously increased from a drain region side to a source region side, and an impurity concentration immediately below the gate electrode in the first conductive type semiconductor region being continuously increased from the source region side to the drain region side in accordance with the germanium concentration in the gate electrode.
A semiconductor device according to a second aspect of the present invention includes: a first conductive type semiconductor portion formed on a semiconductor substrate; a gate electrode formed to surround a side portion of the first conductive type semiconductor portion; a channel region formed in the first conductive type semiconductor portion surrounded by the gate electrode; and source and drain layers formed to cover an upper surface and a lower surface of the first conductive type semiconductor portion, the gate electrode being formed of polycrystalline silicon-germanium, in which a germanium concentration is increased from a drain layer side to a source layer side, and an impurity concentration in the channel region being increased from the source layer side to the drain layer side.
A semiconductor device according to a third aspect of the present invention includes:
a first MISFET including: a first conductive type first semiconductor region formed in a semiconductor substrate; a first gate electrode formed on the first conductive type first semiconductor region; a first channel region formed immediately below the first gate electrode in the first conductive type first semiconductor region; and a second conductive type first diffusion layer constituting source/drain regions formed at opposite sides of the first channel region in the first conductive type first semiconductor region; and
a second MISFET including: a second conductive type second semiconductor region formed in the semiconductor substrate and isolated from the first conductive type first semiconductor region; a second gate electrode formed on the second conductive type second semiconductor region; a second channel region formed immediately below the second gate electrode in the second conductive type second semiconductor region; and a first conductive type second diffusion layer constituting source/drain regions formed at opposite sides of the second channel region in the second conductive type second semiconductor region,
the first and second gate electrodes being formed of polycrystalline silicon-germanium, in which a germanium concentration is continuously increased from a drain region side to a source region side, and an impurity concentration immediately below the first gate electrode in the first conductive type first semiconductor region being continuously increased from the source region side to the drain region side in accordance with the germanium concentration in the first gate electrode.
REFERENCES:
patent: 6630720 (2003-10-01), Maszara et al.
patent: 2003/0146494 (2003-08-01), Puchner et al.
Fukui Hironobu
Ohuchi Kazuya
Jackson Jerome
Kabushiki Kaisha Toshiba
Nguyen Joseph
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