Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2002-08-06
2004-03-23
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S306000, C257S310000, C257S324000, C257S637000, C257S790000, C438S239000, C438S243000
Reexamination Certificate
active
06710422
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims priority of Japanese Patent Application No. 2002-1675, filed in Jan. 8, 2002, the contents being incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, a semiconductor device having conductive plugs for connecting a capacitor and a conductive pattern and a method of manufacturing the same.
2. Description of the Prior Art
The ferroelectric capacitor constituting the FeRAM (Ferroelectric Random Access Memory), which is currently mass-produced, has such a structure that wirings are connected onto both the lower electrode and the upper electrode, i.e., the planar structure. In the ferroelectric capacitor having the planar structure, the contact area of the lower electrode is shaped to protrude from the side of the ferroelectric film.
Corresponding to the requirements of the higher integration of the FeRAM, the capacitor having the stacked structure, which is able to reduce the memory cell area smaller, is being developed. The stacked structure is the structure in which the conductive plug is connected to the undersurface of the lower electrode of the ferroelectric capacitor.
Next, steps of forming the capacitor having the stacked structure is explained with reference to
FIGS. 1A
,
1
B, and
1
C.
First, steps required until the structure shown in
FIG. 1A
is obtained will be explained hereunder.
MOS transistors
102
are formed on a silicon substrate
101
, and then a first interlayer insulating film
103
for covering the MOS transistors
102
is formed.
The MOS transistors
102
are formed on the silicon substrate
101
in a well region
105
that is surrounded by an element isolation layer
104
. Each of the MOS transistors
102
has a gate electrode
102
b
formed on the silicon substrate
101
via a gate insulting film
102
a
, and impurity diffusion regions
102
c
serving as source/drain formed on both sides of the gate electrode
102
b
in the well region
105
. Also, insulating sidewalls
106
used to form high concentration impurity regions
102
d
in the impurity diffusion regions
102
c
are formed on both side surfaces of the gate electrode
102
b.
First contact holes
103
a
are formed in the first interlayer insulating film
103
on one impurity diffusion regions
102
c
of the MOS transistors
102
, and then a first contact plug
107
is buried in the first contact holes
103
a
respectively.
The material constituting the first contact plug
107
is the same as that constituting other contact plugs (not shown) that are not connected to the lower electrode of the capacitor. For example, in Patent Application Publication (KOKAI) 2001-44376, the contact plug connected to the lower electrode of the capacitor and the contact plug not connected to the lower electrode of the capacitor are formed of tungsten or polysilicon that is formed by the same step.
Then, a first metal film
108
, a ferroelectric film
109
, and a second metal film
110
are formed sequentially on the first contact plugs
107
and the first interlayer insulating film
103
.
Then, as shown in
FIG. 1B
, the first metal film
108
, the ferroelectric film
109
, and the second metal film
110
are patterned by using a hard mask continually, so that the first metal film
108
is shaped into a lower electrode
108
a
of a capacitor
111
, the ferroelectric film
109
is shaped into a ferroelectric film
109
a
of the capacitor
111
, and the second metal film
110
is shaped into an upper electrode
110
a
of the capacitor
111
. In this case, the capacitor
111
is the stacked-type capacitor, and the lower electrode
108
a
is connected to one impurity diffusion region
102
c
of the MOS transistor
102
via the underlying first contact plug
107
.
Then, as shown in
FIG. 1C
, a capacitor protection film
112
is formed on the capacitors
111
and the first interlayer insulating film
103
, and then a second interlayer insulating film
113
is formed on the capacitor protection film
112
. Then, a second contact hole
113
a
is formed on the other impurity diffusion regions
102
c
of the MOS transistors
102
by patterning the second interlayer insulating film
113
, the capacitor protection film
112
and the first interlayer insulating film
103
by virtue of the photolithography method. Then, a second contact plug
114
is formed in the second contact hole
113
a
. This second contact plug
114
is formed to connect the bit line (not shown), which is formed on the second contact plug
114
, and the impurity diffusion regions
102
c.
Meanwhile, in many cases the FeRAM is mounted mixedly with the logic semiconductor device. As the embedded device in which the FeRAM and the logic circuit are mixed, there are the security associated chip which requires the authentication and the IC card employed in the local self-governing body.
In the logic semiconductor device, the tungsten plug is employed as the plug to connect the underlying conductive pattern and the overlying conductive pattern, and in addition the resistance value of the tungsten plug is employed as the spice parameter used to design the circuit.
Accordingly, in the sense to utilize the circuit design resource accumulated up to this time and reduce the developmental man-hour and cost, the logic-embedded FeRAM needs the tungsten plug.
By the way, various heat treatments such as the crystallizing annealing, the recovery annealing, or the like are needed in the oxygen containing atmosphere to form the ferroelectric capacitor. Typically the RTA (Rapid Thermal Annealing) process is carried out at 750° C. for 60 seconds as the annealing for crystallizing the ferroelectric film. Also, after the formation of the capacitor, the film quality recovery annealing of the ferroelectric film is carried out in the furnace at 650° C. for 60 minutes.
Here, as shown in
FIGS. 1B and 1C
, if the tungsten plug is employed as the first contact plugs
107
formed immediately under the lower electrodes
108
a
of the capacitors
111
, the tungsten plug is oxidized at the very high speed and at the low temperature in the annealing process in the oxygen containing atmosphere.
When the tungsten plug starts to oxidize, such oxidation spreads over the entire plug. Thus, the contact failure of the lower electrode easily occurs, so that the reduction in yield of the FeRAM device is caused. Such oxidation of the tungsten plug is also set forth in Patent Application Publication (KOKAI) Hei 10-303398. In order to keep the normal contact by preventing the oxidation of the tungsten plug, the heating temperature in the annealing process of the capacitor must be lowered much more.
Therefore, the improvement in performance of the ferroelectric capacitor and the improvement in contact performance of the tungsten plug are in the trade-off relationship.
As described above, the second contact hole
113
a
for connecting the bit line and the impurity diffusion regions is opened after the capacitors
111
and the second interlayer insulating film
113
are formed. This is because, if the second contact hole for the bit line connection is formed in the first interlayer insulating film
103
simultaneously with the first contact hole
103
a
, the upper surface of the tungsten plug formed in the second contact hole is exposed after the formation of the capacitor and then oxidized.
However, the aspect ratio of the second contact hole
113
a
shown
FIG. 1C
is increased with the future miniaturization of the FeRAM. Thus, the etching technology for forming the second contact hole
113
a
, the formation of the glue layer acting as the underlying layer before the tungsten is buried in the second contact hole
113
a
, etc. should be improved.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device capable of improving a yield of a contact plug formed directly under the capacitor lower electrode and also facilitating the d
Hikosaka Yukinobu
Itoh Akio
Saito Takeyasu
Takai Kazuaki
Armstrong Kratz Quintos Hanson & Brooks, LLP
Fujitsu Limited
Wojciechowicz Edward
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