Active solid-state devices (e.g. – transistors – solid-state diode – Schottky barrier – Specified materials
Reexamination Certificate
2001-12-19
2003-06-03
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Schottky barrier
Specified materials
C438S163000, C438S197000, C438S230000, C438S595000, C257S315000, C257S316000, C257S317000, C257S369000
Reexamination Certificate
active
06573583
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-397293, filed Dec. 27, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND
1. Field of the Invention
In recent years, shrinking of a CMOS-type semiconductor device is being promoted in compliance with the request for the high-speed operation and the high-performance of the device. In accordance with progress in the shrinking, the scaling of the distance between the gate and the source/drain contact is required.
2. Description of the Related Art
The problems relating to the shrinking of the high-performance MOS transistor equipped with a silicide electrode will now be described.
FIG. 1A
is a cross-sectional view showing the construction of a high-performance MOS transistor equipped with a silicide electrode. The MOS transistor shown in
FIG. 1A
comprises a Si substrate
101
, a device isolation insulating film
102
of a shallow trench isolation (STI), a gate electrode formed of a polycrystalline silicon (polysilicon) film
106
formed on the Si substrate
101
with a gate insulating film
105
interposed therebetween, a shallow source/drain diffusion layer
107
formed by ion implantation with the gate electrode used as a mask, a gate side-wall insulating film
109
formed on the side-wall of the gate electrode, a deep source/drain diffusion layer
111
of a high impurity concentration formed by ion implantation with the gate electrode equipped with the gate side-wall insulating film
109
used as a mask, and a metal silicide layer
112
such as a cobalt silicide layer formed on the exposed surface of the deep source/drain diffusion layer
111
of a high impurity concentration and on the gate electrode formed of the polysilicon layer
106
. A mark S
1
shown in
FIG. 1A
denotes the length showing the expansion in the direction of the gate length of the metal silicide film covering the deep source/drain diffusion layer
111
of a high impurity concentration.
In shrinking the semiconductor device, it is absolutely necessary to decrease the width of the gate side-wall insulating film
109
in accordance with the scaling. Also, it is necessary to increase to some extent the depth of the deep source/drain diffusion layer
111
of a high impurity concentration in view of the generation of the leakage current in the junction surface between the deep source/drain diffusion layer
111
of a high impurity concentration having the silicided surface and the Si substrate
101
. If the width of the gate side-wall insulating film
109
is decreased in this case, it is impossible to suppress the short-channel effect produced by the deep source/drain diffusion layer
111
of a high impurity concentration, with the result that it is difficult to shrink the width of the gate side-wall by the scaling in the high-performance MOS transistor equipped with a silicide electrode.
On the other hand, if the distance S
1
between the edge of the gate side-wall insulating film
109
and the peripheral portion on the side of the source/drain of the device isolation insulating film
102
of STI is decreased by the scaling, the area of the metal silicide layer formed on the deep source/drain diffusion layer of a high impurity concentration is decreased so as to increase the parasitic resistance. Particularly, in the case of using the MOS transistor structure of a corner contact type, in which a contact hole is formed in the corner portion of the source/drain forming region, the increase in the parasitic resistance constitutes a serious problem.
In conjunction with the problem described above, the method of forming a contact hole for connecting the source/drain regions of a high-performance MOS transistor equipped with a silicide electrode to the wiring on the semiconductor substrate and the problems accompanying the forming method will now be described in detail with reference to FIG.
1
B.
FIG. 1B
is a cross-sectional view showing the step of forming a contact hole in a high-performance MOS transistor equipped with a silicide electrode. As shown in the drawing, an interlayer insulating film
118
is formed to cover a high-performance MOS transistor equipped with silicide electrodes isolated from each other by the device isolation insulating film
102
of STI, followed by forming a contact hole
119
in the interlayer insulating film
118
by aligning a mask with the metal silicide layer
112
on the deep source/drain diffusion layer of a high impurity concentration by using a resist (not shown) and lithography.
In this case, if the length S
1
shown in
FIG. 1A
is shrunk by the scaling, a mask misalignment is generated as shown in
FIG. 1B
, with the result that the contact hole
119
partly reaches the gate side-wall insulating film
109
so as to markedly decrease the distance S
2
corresponding to the contact area with the metal silicide layer
112
.
The connection between the metal wiring (not shown) on the semiconductor substrate and the metal silicide layer
112
is achieved by burying a contact plug made of a metallic material in the contact hole
119
. Therefore, if the distance S
2
is decreased, the parasitic resistance between the source and drain of the MOS transistor is increased so as to lower the operating speed.
Also, with progress in the development of the semiconductor device, it is necessary to make shallower not only the shallow source/drain diffusion layer
107
of the MOS transistor but also the deep source/drain diffusion layer
111
of a high impurity concentration. However, as described previously, if the source/drain diffusion layer
111
of a high impurity concentration is made shallower, the generation of the contact leakage in forming the silicide layer
112
and the increase in the power consumption of the CMOS circuit accompanying the generation of the contact leakage are brought about as new problems. As a measure for overcoming these problems, proposed is a MOS transistor of an elevated source/drain structure.
The MOS transistor of this type is constructed such that a single crystal Si or SiGe layer is formed selectively by means of an epitaxial growth on a source/drain diffusion region of a high impurity concentration, and the impurity concentration in the surface region of the Si substrate including the epitaxial growth layer is increased so as to make the high impurity concentration diffusion layer in the Si substrate substantially shallower.
In the case of using the elevated source/drain structure, the surface region of the single crystal Si or SiGe layer grown by the selective epitaxial method on the source/drain diffusion region is converted into a silicide region so as to make it possible to avoid the generation of the contact leakage current.
In applying the elevated source/drain structure, it is absolutely necessary in allowing the CMOS circuit to operate normally to ensure the device isolation characteristics of STI so as to prevent completely a single crystal Si or SiGe layer from growing on the upper surfaces of the device isolation insulating film
102
of STI and the gate side-wall insulating film
109
and to allow the epitaxial growth layer to be formed selectively only on the upper surface of the source/drain diffusion region.
However, in the STI having a small separation width, the buried state is rendered poor when the device isolation insulating film
102
is buried in the trench so as to generate a seam of the device isolation insulating film in the central portion of the trench width in the longitudinal direction of the trench, as described in, for example, Jpn. Pat. Appln. KOKAI Publication No. 58-143548 and Jpn. Pat. Appln. KOKAI Publication No. 1-151245. In this case, if the epitaxial growth layer is selectively formed on the source/drain diffusion region, Si or SiGe particles are generated in the central portion in the width direction of the STI with the portion of the seam providing the growth nucleus.
The failure generation of the device isolation characte
Kabushiki Kaisha Toshiba
Nelms David
Pillsbury & Winthrop LLP
Tran Mai-Huong
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