Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – With peripheral feature due to separation of smaller...
Reexamination Certificate
2001-05-15
2003-08-05
Elms, Richard (Department: 2824)
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
With peripheral feature due to separation of smaller...
C257S738000, C257S778000, C257S795000
Reexamination Certificate
active
06603191
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2000-146012, filed May 18, 2000; and No. 2000-147245, filed May 19, 2000, the entire contents of both of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device of a CSP (Chip Size Package) structure and a method of manufacturing the same.
2. Description of the Related Art
In compliance with requests for miniaturization and reduction in the thickness of electronic appliances, a semiconductor device of a CSP (Chip Size Package) structure, in which the size of a semiconductor chip is rendered substantially equal to the size of a package, has come to be widely used. A method of manufacturing a semiconductor device of this type will now be described with reference to
FIGS. 19
to
22
.
In the first step, a plurality of connection pads
2
consisting of, for example, aluminum electrodes are formed on a front surface (circuit surface) of a silicon wafer (semiconductor wafer)
1
, followed by forming a protective covering film (not shown) consisting of, for example, silicon oxide or silicon nitride on the entire front surface of the silicon wafer
1
except the central portion of each of the connection pads
2
, as shown in FIG.
19
. Then, a front side protective film
3
is formed on the protective covering film except the central portion of each of the connection pads
2
.
For forming the front side protective film
3
, the entire surface on the side of the circuit surface of silicon wafer
1
is coated with, for example, a polyimide-based resin material, followed by curing the resin coating and subsequently applying a resist patterning and a protective film patterning by using an etchant. Then, the resist is peeled off so as to form the front side protective film
3
.
In the next step, a wiring
5
is formed on each of the connection pads
2
exposed to the outside via an open portion
4
formed in the front side protective film
3
. As described herein later, the wiring
5
is formed in a manner to be connected to each of columnar electrodes
6
. As a result, it is possible to arrange the columnar electrodes
6
to form a matrix in the central portion of the wafer so as to increase the pitch of the connection pads
2
formed in the peripheral portion alone of each semiconductor device, to increase the electrode area, to increase the bonding strength with a circuit substrate, and to improve the reliability of the connection.
After formation of the wiring
5
, a plurality of columnar electrodes
6
are formed in predetermined positions on the wirings
5
. For forming the columnar electrode
6
, a resist (not shown) for forming the columnar electrode is coated in a thickness of, for example, 100 to 150 &mgr;m, followed by curing the coated resist. Then, a resist patterning is applied, followed by applying an electroplating to the open portion formed by the resist patterning treatment so as to form the columnar electrode
6
.
In the next step, the entire surface of the silicon wafer
1
including the columnar electrodes
6
is molded with a resin material such as an epoxy resin so as to form a sealing film
7
slightly thicker than the columnar electrode
6
, as shown in FIG.
20
. Further, after the sealing film
7
is cured, the resultant silicon wafer
1
is moved onto a grinding process table (not shown) so as to have the front side of the sealing film
7
polished by a grinding apparatus, with the result that an edge surface
61
of the columnar electrode
6
is exposed to the outside on the upper surface of the sealing film, as shown in FIG.
21
. Still further, the back surface of the silicon wafer
1
is polished by the grinding process so as to decrease the thickness of the silicon wafer
1
to a predetermined level. Then, a process of marking the article number and the lot number is applied to the polished back surface of the silicon wafer
1
.
In the next step, the silicon wafer
1
is disposed on a dicing tape (not shown) mounted to a dicing frame, with the back surface of the silicon wafer
1
facing downward, followed by cutting the silicon wafer
8
along cut lines
8
, as shown in
FIG. 22
, so as to obtain individual semiconductor devices
10
each fixed to the semiconductor substrate for each chip.
In the conventional semiconductor device
10
manufactured as described above, the sealing film
7
is formed first on the silicon wafer
1
, followed by cutting the silicon wafer
1
along the cut lines
8
. It follows that a side surface
1
a
including the cut surface of each of the separated semiconductor devices
10
and the back surface of each separated semiconductor device
10
are exposed to the outside. As a result, serious problems are generated. For example, water or moisture permeates into the boundary region between the sealing film
7
and the front side protective film
3
in the exposed surface so as to oxidize the wiring
5
. Also, cracks are generated between the sealing film
7
and the front side protective film
3
so as to lower the reliability. In addition, since the semiconductor substrate is exposed to the outside, the semiconductor substrate tends to be broken in, for example, handling the semiconductor substrate.
BRIEF SUMMARY OF THE INVENTION
The present invention is directed to a semiconductor device of, for example, a CSP structure, which is obtained by cutting a semiconductor wafer, and is intended to provide a semiconductor device in which a protective film is formed to cover at least the cut surface of the semiconductor substrate so as to improve the reliability, and to provide a method of manufacturing the particular semiconductor device.
According to a first aspect of the present invention, which permits achieving the above-noted object, there is provided a semiconductor device comprising a semiconductor substrate including a front surface having a plurality of connection pads formed thereon, a back surface opposite to the front surface, and a side surface positioned between the front surface and the back surface; and a front side protective film having open portions exposing the plural connection pads formed on the front surface of the semiconductor substrate to the outside and formed to cover the side surface of the semiconductor substrate.
According to a second aspect of the present invention, which permits achieving the above-noted object, there is provided a method of manufacturing a semiconductor device, comprising the steps of preparing a silicon wafer including a plurality of chip forming regions each provided with a plurality of connection pads on its front surface; separating the silicon wafer into individual chip forming regions so as to form a plurality of semiconductor substrates arranged a predetermined distance apart from each other; forming a front side protective film covering the front surface of each of the semiconductor substrates, having open portions formed to expose the plural connection pads to the outside, and filling the clearance among the plural semiconductor substrates; and cutting each of the semiconductor substrates with a width smaller than the clearance between the semiconductor substrates.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.
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patent: 0 706 208 (1996-04-0
Kuwabara Osamu
Wakabayashi Takeshi
Casio Computer Co. Ltd.
Elms Richard
Frishauf Holtz Goodman & Chick P.C.
Menz Douglas
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