Semiconductor device, and method of manufacturing the same

Details Semiconductor device, and method of manufacturing the same Semiconductor device, and method of manufacturing the same

2001-05-29

2003-06-03

Nguyen, Ha Tran (Department: 2812)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S760000

Reexamination Certificate

active

06573603

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having a multilayer interconnection provided on a semiconductor substrate, the interconnection comprising a lower wiring layer and an upper wiring layer, as well as to a method of manufacturing the semiconductor device.
2. Background Art
In a semiconductor device having a multilayer interconnection, a spin-on-glass (SOG) film is used as an interlayer dielectric film for improving flatness of a wafer. After having been formed in conjunction with a solvent by means of spin coating, the SOG film is subjected to heat treatment, whereby the SOG is used as an interlayer dielectric film (SiO) of superior flatness.
A related-art semiconductor device of this type and a method of manufacturing the semiconductor device will be described.
FIGS. 5 through 11
are cross-sectional views showing the related-art semiconductor device and a method of manufacturing the same in sequential order of processes for manufacturing.
In the process shown in
FIG. 5
, lower wiring layers
3
are formed over a dielectric film
2
which covers a semiconductor substrate
1
having desired circuit elements formed thereon. Further, a dielectric layer
4
is formed so as to cover the lower wiring layers
3
.
In the process shown in
FIG. 6
, an SOG film
5
is formed on the dielectric film
4
. The SOG film
5
is for making irregularities formed between the lower wiring layers
3
smooth. However a minute projection
6
of about 0.1 &mgr;m often arises in the surface of the SOG film
5
during the course of formation of the SOG film
5
.
In the process shown in
FIG. 7
, a silicon oxide film
7
is formed so as to cover the surface of the SOG film
5
. The silicon oxide film
7
is formed for imparting a desired thickness to the dielectric film
4
formed on the lower wiring layers
3
, by means of the CVD method. A projection
8
of much greater size is formed at a position on the silicon oxide film
7
corresponding to the minute projection
6
, so as to reflect the geometry of the minute projection
6
. The projection
8
impairs the flatness of the dielectric film
4
. Reference numeral
9
designates a skirt portion of the projection
8
. Broken lines extending from the skirt
9
to the minute projection
6
represent derivation of the projection
8
from enlargement of the minute projection
6
. In the projection
8
, the silicon oxide film
7
has rough composition.
In the process shown in
FIG. 8
, a photoresist film
10
is formed on the silicon oxide film
7
, and the photoresist film
10
is patterned, with the result that two openings
10
a
and
10
b
are formed in the photoresist film
10
, as shown in the drawing. These openings
10
a
and
10
b
are for forming interconnection holes to be used for interconnecting the lower wiring layers
3
to the upper wiring layer. The drawing illustrates the opening
10
b
formed at a position in the photoresist film
10
where the projection
8
is present and the opening
10
a
formed at a position in the photoresist film
10
where no projection
8
is present.
Subsequently, interconnection holes
11
are formed in the respective openings
10
a
and
10
b.
As shown in
FIGS. 9 and 10
, the interconnection holes
11
are formed through two processes. As shown in
FIG. 9
, in the first of the processes, enlarged openings
12
are formed in an upper portion of the silicon oxide film
7
. As shown in
FIG. 10
, in the second of the processes, through holes
13
are formed so as to reach the corresponding lower wiring layers
3
.
There has hitherto been known a failure such that step coverage of an upper wiring layer is deteriorated when the aspect ratio (i.e., the ratio of hole depth to hole diameter) of the interconnection hole
11
is large. The enlarged openings
12
are formed for reducing the aspect ratio in order to prevent occurrence of such a failure. The enlarged openings
12
are formed by means of wet-etching the silicon oxide film
7
through the openings
10
a
and
10
b
of the photoresist film
10
. The enlarged openings
12
are wider (of greater diameter) than the openings
10
a
and
10
b.
A normal enlarged opening
12
is formed below the right-side opening
10
a
shown in
FIG. 9. A
modified/enlarged opening
12
A is formed below the left-side opening
10
b
shown in FIG.
9
. The portion of the silicon oxide film
7
located at the projection
8
has rough composition and a higher etch rate for wet-etching than do the other portions of the silicon oxide film
7
. Hence, a resultant enlarged opening
12
A is deformed. More specifically, the projection
8
has a higher etch rate, and hence the projection
8
located below the opening
10
b
is etched fast, with the result that an etchant reaches the SOG film
5
. The SOG film
5
is also etched. Reference numeral
12
a
designates an etched portion of the SOG film
5
.
In the second process for forming the interconnection holes
11
, the silicon oxide film
7
is subjected to dry-etching by way of the openings
10
a
and
10
b
of the photoresist film
10
. As shown in
FIG. 10
, a through hole
13
continually extending from the enlarged opening
12
and another through hole
13
continually extending from the enlarged opening
12
A are formed. The through holes
13
have substantially the same width (diameter) as do the openings
10
a
and
10
b
of the photoresist film
10
, thereby uncovering predetermined portions of the respective lower wiring layers
3
.
In the process shown in
FIG. 11
, upper wiring layers
14
are formed. The upper wiring layers
14
are formed by means of forming a conductor layer on the silicon oxide film
7
from which the photoresist film
10
has been removed, and patterning the conductor layer. The right-side upper wiring layer
14
shown in
FIG. 11
is normally connected to the lower wiring layer
3
by way of the interconnection hole
11
. In contrast, anomalies have arisen in a left-side upper wiring layer
14
A. The upper wiring layer
14
A is susceptible to failures which would have considerably adverse effect on the reliability of an interconnection, such as occurrence of a break
14
a
in the interconnection hole
11
, deterioration of step coverage, issuance of a gas from an etched portion
12
a
of the SOG film during the course of formation of the upper wiring layer
14
, and degradation of quality of the upper wiring layer
14
.
In Japanese Patent Application Laid-Open No. 69560/1997, formation of a silicon nitride film on an SOG film and formation of a silicon oxide film on the silicon nitride film are proposed for preventing etching of the SOG film, which would otherwise be caused by variations in the thickness of the silicon oxide film on the SOG film and variations in etch rate at which the silicon oxide film is wet-etched.
However, variations in the depth of an enlarged opening ascribable to variations in wet-etching of a silicon oxide film cannot be eliminated by the proposed technique. Formation of an interconnection hole cannot be controlled correctly, thereby degrading the reliability of a multilayer interconnection.
SUMMARY OF THE INVENTION
The present invention proposes a semiconductor device which obviates the previously-described inconvenience, enables more correct formation of an interconnection hole for interconnecting an upper wiring layer to a lower wiring layer, and improves the reliability of multilayer wiring, as well as a method of manufacturing the semiconductor device.
According to one aspect, the present invention provides a semiconductor device comprising a lower wiring layer provided on a semiconductor substrate, a spin-on-glass (SOG) film covering the lower wiring layer, a lower silicon oxide film formed on the SOG film, a silicon nitride film formed on the lower silicon oxide film, an upper silicon oxide film formed on the silicon nitride film, and an upper wiring layer provided on the upper silicon oxide film. Further the upper wiring layer is connected to the lower wiring layer by way of enlarged openings

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