Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Junction field effect transistor
Reexamination Certificate
2000-10-05
2003-05-27
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Junction field effect transistor
C257S664000, C257S728000, C257S758000
Reexamination Certificate
active
06570199
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and more particularly to the semiconductor device provided with a conductive path having a stacked structure.
2. Description of the Related Art
In a conventional semiconductor device such as an MMIC (Monolithic Microwave Integrated Circuit), conductive paths functioning as signal lines to connect circuit devices electrically and to transmit a high-frequency signal are formed on a semiconductor substrate made of, for example, GaAs (Gallium Arsenide) on which the circuit devices including active elements such as an FET (Field Effect Transistor) or a like or passive elements such as an inductor, capacitor, bonding pad or a like are mounted. The signal line, together with the semiconductor substrate on which the signal line is formed and with a dielectric composed of an insulating film formed between the semiconductor substrate and the signal line, constitutes a microstrip line. As the signal line constituting the microstrip line, the conductive path having a wiring structure, for example, in two layers up and down (that is, one above the other) is mounted.
Configurations of a conventional conductive path functioning as the signal line formed on the semiconductor device such as the MMIC will be hereinafter described by referring to
FIGS. 7 and 8
.
FIG. 7
is a top view of a conventional microstrip line
400
having the signal line constructed in two layers up and down. Configurations of the conductive path functioning as the signal line of the microstrip line
400
will be described by referring to
FIG. 8
which is a cross-sectional view of the signal line of
FIG. 7
taken along the line D—D.
As shown in
FIG. 8
, on a substrate
402
made, for example, of GaAs is formed a first interlayer dielectric
404
having an approximately uniform thickness and at a predetermined place on the first interlayer dielectric
404
is formed a lower layer wiring
406
by a deposition method. At portions being exposed from the lower layer wiring
406
stacked on the first interlayer dielectric
404
and on the lower layer wiring
406
is formed a second interlayer dielectric
408
. In the second interlayer dielectric
408
is formed a contact hole
410
so that the lower layer wiring
406
is partially exposed. At a predetermined place including portions of the contact hole
410
on the second interlayer dielectric
408
is formed an upper layer wiring
412
by a plating method and the upper layer wiring
412
is electrically connected through the contact hole
410
to the lower layer wiring
406
. At portions being exposed from the upper layer wiring
412
stacked on the second interlayer dielectric
408
and on the upper layer wiring
412
is formed a passivation film
414
. The upper layer wiring
412
described above is formed by a known lift-off method by using a resist film for forming an upper layer wiring (not shown). That is, first, the resist film is formed on the second interlayer dielectric
408
. Then, patterning is performed on the resist film so as to form an aperture trench corresponding to the upper layer wiring
412
. A metal for the upper wiring is embedded by the plating method and then the resist film together with unwanted metal accumulated on the resist film is removed. Therefore, the thickness of the upper layer wiring is determined by the thickness of the resist film for forming the upper layer wiring described above.
In the conventional conductive path functioning as the signal line, its resistance is made low by constructing the signal line so as to have the wiring structure stacked in two layers up and down, by forming the resist film for forming the upper layer wiring so as to have the large thickness and thus by forming the upper layer wiring having the thickness being as large as possible.
However, the conventional signal line has problems. That is, when the lift-off method is employed, since working accuracy is limited by a ratio of a width of the aperture trench to its depth (i.e., aspect ratio), limits are imposed on the thickness of the resist film for forming the upper layer wiring, i.e., on the thickness of the upper layer wiring. Because of this, in the case of, for example, a high-power MMIC, the conventional wiring structure poses serious limitations to the method in which a direct current resistance is made low by increasing the thickness of the upper layer wiring, thus actually making it impossible to fully lower the direct current resistance. Another problem with the conventional conductive path is that, when a high-frequency signal is transmitted, due to a skin effect that a current flows only on a surface of a conductor, even if an area of cross-section is made larger simply by increasing the thickness of the upper layer wiring, a resistance against high-frequency currents cannot be lowered practically.
SUMMARY OF THE INVENTION
In view of the above, it is an object of the present invention to provide a semiconductor device capable of sufficiently lowering an electrical resistance in a conductive path functioning as a signal line. It is another object of the present invention to provide a method for manufacturing, comparatively easily, the semiconductor device capable of sufficiently lowering the electrical resistance in the conductive path functioning as the signal line. It is still another object of the present invention to provide the semiconductor device capable of sufficiently lowering the electrical resistance in high-frequency signals in the conductive path.
According to a first aspect of the present invention, there is provided a semiconductor device including:
a semiconductor substrate;
a circuit device mounted on the semiconductor substrate;
an insulating film covering the circuit device; and
a conductive path used for the circuit device mounted on the insulating film,
whereby the conductive path has a stacked structure composed of a plurality of conductive layers and of interlayer dielectrics interposed among the conductive layers and allowing a partial connection among the conductive layers, and each of the conductive layers has approximately the same thickness.
In the foregoing, a preferable mode is one wherein the conductive path constitutes a part of a microstrip line being suitable for high-frequency currents.
Also, a preferable mode is one wherein a pin hole is formed in the interlayer dielectric which passes through the interlayer dielectric in a direction of its thickness and the conductive layers formed on both sides of the interlayer dielectric are connected to each other through the pin hole.
According to a second aspect of the present invention, there is provided a method for manufacturing a semiconductor device having a semiconductor substrate, a circuit device formed on the semiconductor substrate, an insulating film covering the circuit device and a conductive path used for the circuit device formed on the insulating film including steps of:
forming the insulating film covering the circuit device formed on the semiconductor substrate;
forming a conductive layer functioning as the conductive path on the insulating film;
forming, on the conductive layer, an interlayer dielectric having a pin hole;
forming, on the interlayer dielectric, other conductive layer being connected to the conductive layer through the pin hole,
repeating, alternately, a process of forming, on the other conductive layer, a new interlayer dielectric having the pin hole and a process of forming, on the interlayer dielectric, a new conductive layer contacting, through the pin hole formed in the interlayer dielectric, the conductive layer disposed at a lower place; and
performing patterning on a stacked body to form the conductive path composed of the stacked body containing the conductive layer and the interlayer dielectric.
In the foregoing, a preferable mode is one wherein each of the interlayer dielectrics is formed so as to have a thickness of several Å to several tens of Å by using a plasma enhanced CVD (Chemical Vapor Deposition)
Crane Sara
Oki Electric Industry Co, Ltd.
Rabin & Berdo P.C.
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