Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Including adhesive bonding step
Reexamination Certificate
2001-10-18
2003-04-22
Fahmy, Wael (Department: 2823)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Including adhesive bonding step
C438S127000, C438S114000, C438S125000
Reexamination Certificate
active
06551862
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device manufacturing technique and more particularly to a technique which is effective in its application to the improvement of mounting temperature cyclicity, reflow characteristic and mounting performance of a semiconductor device.
As an example of a semiconductor device (semiconductor package) having a semiconductor chip with a semiconductor integrated circuit formed thereon, further having bump electrodes (solder balls) as external terminals and a chip supporting substrate for supporting the semiconductor chip, there is known a semiconductor device called BGA (Ball Grid Array).
In a certain type of a BGA intended for the reduction of wall thickness there is used a tape substrate (wiring board) as a semiconductor chip supporting substrate.
In assembling the BGA, a semiconductor chip is mounted on one side, i.e., a chip supporting surface, of the tape substrate with use of an insulating adhesive, and after wire bonding, sealing is performed with resin to form a sealing portion.
Further, at the back of the tape substrate, solder balls (external terminals) are mounted on bump lands as external terminal mounting electrodes (a solder paste may be printed and thereafter melted by reflow for example).
Therefore, in the case of a BGA of a structure wherein solder balls are arranged in both inside and outside areas of a semiconductor chip, a stress is apt to be imposed on a bonded portion of the solder balls arranged near a peripheral edge of the semiconductor chip due to a difference in thermal expansion coefficient among the semiconductor chip, tape substrate, and mounting substrate.
As a technique for relieving stress between a semiconductor chip and a chip supporting substrate there is described in Japanese Unexamined Patent Publication No. 2000-114424 a technique wherein a relatively hard adhesive layer is disposed on a substrate side (lower side) between a semiconductor chip and a chip supporting substrate and a layer lower in Young's modulus than the adhesive layer is disposed on the chip side (upper side) which overlies the adhesive.
In Japanese Unexamined Patent Publication No. Hei 11(1999)-224912 there is described a technique wherein a tent-like tension is ensured by a layer of a high elastic modulus at the time of bonding to a wiring board while maintaining a stress relieving structure with use of a layer of a low elastic modulus, thereby utilizing a space surrounded by wiring lines, wiring board and the high elastic modulus layer as a vent line to ensure an anti-package crack characteristic.
SUMMARY OF THE INVENTION
However, in the semiconductor package described in the above Japanese Unexamined Patent Publication No. 2000-114424, a hard adhesive layer is disposed on the lower side (substrate side) between the semiconductor chip and the chip supporting substrate and a layer of a low Young s modulus is disposed on the upper side (chip side), so when pressure based on a resin injection pressure in resin molding is applied to the semiconductor chip from above, the chip sinks and buckles, with consequent occurrence of a chip crack.
In the publication in question, moreover, there is found no description about an air vent portion for the escape of inside air to the outside. Even if an air vent portion is formed in the chip supporting substrate, air is difficult to escape to the exterior because a hard adhesive layer is disposed on the lower side. Therefore, the internal pressure of the package rises due to steam and outgas generated by heat treatment at the time of mounting the semiconductor device onto the mounting substrate, such as reflow of solder bumps, so that defects such as package crack, peeling, swelling, and popcorn phenomenon are apt to occur, thus giving rise to the problem that the reliability (reflow characteristic) in reflow (mounting) is poor.
According to a semiconductor package described in Japanese Unexamined Patent Publication No. Hei 11(1999)-224912, the foregoing vent line has a tubular structure larger in diameter than a filler (to 3 &mgr;m) contained in the sealing resin for example, thus allowing the molding resin to get into the vent line at the time of resin sealing. Once the molding resin gets into the vent line, not only the vent line loses its venting function, but also there is a fear that an unfilled area may remain in the resin in the course of the molding resin getting into the vent line which is complicated in structure. Such an unfilled area left in the resin rises in its internal pressure at the time of reflow, which can cause a popcorn phenomenon.
In the case of a BGA using a tape substrate as a chip supporting substrate, there occurs a warp of a package due to shrinkage during curing of a molding resin which is attributable to a difference in thermal expansion coefficient among the molding resin, a semiconductor chip and the tape substrate or insufficient rigidity of the tape substrate.
The resulting deterioration of the mounting performance poses a problem.
Further, stress is apt to concentrate in bonded portions on the package side and the mounting substrate side of solder balls arranged near a peripheral edge portion of the semiconductor chip, thus giving rise to the problem that there occurs a defective connection in a mounting temperature cycle test.
It is an object of the present invention to provide a semiconductor device and a method of manufacturing the same, which can improve the mounting temperature cyclicity.
It is another object of the present invention to provide a semiconductor device and a method of manufacturing the same, which can improve the reflow characteristic.
It is a further object of the present invention to provide a semiconductor device and a method of manufacturing the same, which can improve the mounting performance.
The above and other objects and novel features of the present invention will become apparent from the following description and the accompanying drawings.
An outline will be given below of typical inventions out of those disclosed herein.
In one aspect of the present invention there is provided a semiconductor device comprising a wiring board, a semiconductor chip disposed on the wiring board, an insulating, first layer disposed between the semiconductor chip and the wiring board, an insulating, second layer disposed between the semiconductor chip and the first layer and formed harder than the first layer, a conductive member for connecting a surface electrode on the semiconductor chip with a corresponding connecting terminal on the wiring board, a sealing portion formed by sealing the semiconductor chip and the conductive member with resin, and a plurality of external terminals disposed on the side opposite to a chip supporting surface of the wiring board.
According to this construction, an insulating die bonding layer composed of the first and second layers between the semiconductor chip and the wiring board can be made thick easily.
Therefore, it is possible to improve the resin balance between the surface and the back of the semiconductor chip. As a result, it is possible to diminish a difference in shrinkage factor among the chip sealing portion on the semiconductor chip, the semiconductor chip, the die bonding layer, and the mounting substrate.
Further, since it is possible to thicken the insulating die bonding layer composed of the first and second layers on the back side of the semiconductor chip, it is possible to diminish the concentration of stress in package-side bonded portions of bump electrodes and mounting substrate-side bonded portions thereof, whereby it is possible to diminish defective connections of bump electrodes in temperature cycle.
Consequently, it is possible to improve the mounting temperature cyclicity (life).
In another aspect of the present invention there is provided a semiconductor device comprising a wiring board, a semiconductor chip disposed on the wiring board, a porous layer as an insulating, first layer disposed between the semiconductor chip and the wiring board, an insulati
Fujisawa Atsushi
Hirano Tsugihiko
Konno Takafumi
Oota Riyouichi
Fahmy Wael
Hitachi , Ltd.
Mattingly Stanger & Malur, P.C.
Pham Thanh V
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