Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2000-10-04
2003-07-29
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S350000, C257S368000, C257S379000, C257S380000, C257S381000, C257S382000, C257S383000, C257S384000, C257S536000, C257S538000
Reexamination Certificate
active
06600210
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device suitable as an input circuit and an output circuit, and particularly relates to a semiconductor device and method of manufacturing the semiconductor device having an improved electrostatic resistance.
2. Background Art
Conventionally, a source diffusion layer and a drain diffusion layer of a transistor constituting an internal circuit of a semiconductor device are formed by a silicide layer in order to reduce the resistance of these layers. Furthermore, since thin film structures have made further advances in recent years, silicide films have been further required not only for the internal circuits but also for transistors constituting the input and output circuits.
FIG. 42
shows a plan view of the conventional semiconductor device and
FIG. 43
shows a cross sectional view along the V—V line in FIG.
42
. In
FIG. 42
, the internal wiring is omitted. Here, the semiconductor device shown in
FIGS. 42 and 43
is referred to as the first conventional example.
In the first conventional example, a P-well
102
is formed on the semiconductor substrate
101
. An element-separating insulating film
103
a
in the form of a ring is selectively formed on a surface of the P-well
102
, and an element-separating insulating film
103
b
is formed on the boundary layer of the P-well
102
formed on the semiconductor substrate
101
.
In an area surrounded by the element-separating insulating film
103
a
, two N channel MOS transistors
11
a
and
11
b
are formed. Three N
+
diffusion layers
104
a
,
104
b
, and
104
c
are formed on the surface of the area surrounded by the element-separating insulating film
103
a
, wherein, the N
+
diffusion layer
104
a
constitutes a source diffusion layer of the MOS transistor
111
a
, the N
+
diffusion layer
104
c
constitutes a source diffusion layer of the N channel MOS transistor, and the N
+
diffusion layer
104
b
constitutes a drain diffusion layer of the N channel MOS transistors
111
a
and
111
b
. That is, the drain diffusion layers of the two N channel MOS transistors
111
a
and
111
b
are united.
A P
+
diffusion layer
105
is formed on an area sandwiched by two element-separating insulating layers
103
a
and
103
b
. Silicide films
106
are formed on the surface of N
+
diffusion layers
104
a
,
104
b
,
10
c
, and P
+
diffusion layer
105
.
Each N channel MOS transistor
111
a
and
111
b
comprises a low concentration diffusion layer
107
, a gate insulating film
108
, a side wall insulating film
109
and a gate electrode
110
. The gate electrode
110
is constituted by laminated polycrystalline silicon films and a silicide film.
Furthermore, an interlayer insulating film
112
is formed covering the N channel MOS transistors
111
a
and
111
b
. Contact holes reaching each silicide films
106
are formed penetrating the interlayer insulating films
112
, and contact plugs
113
are embedded inside those contact holes. Wiring
114
is formed at each contact hole
113
.
Since silicide films
106
are formed in conventional semiconductor devices for reduction of the circuit resistance, a problem arises that the conventional input circuits as well as the output circuits are liable to be affected by external electrostatic discharge (ESD), and the electrostatic resistance (resistance to surges) of these circuits decreases.
Japanese Patent (Granted) Publications No. 2773220 and No. 2773221 disclose a semiconductor device in which a region in a portion of the diffusion layer between the source and the drain is left without forming the silicide film. This type of the conventional example is hereinafter referred to as the second conventional example.
FIG. 44
is a plan view showing the structure of the second conventional example, and
FIG. 45
is the cross-sectional view of along the W—W line in FIG.
44
. Here, the same elements of the second conventional example shown in
FIGS. 44 and 45
as those shown of the first convention example shown in
FIGS. 43 and 45
are denoted by the same reference numerals and their explanations are omitted.
In the second conventional example, a mask insulating film
118
is formed between the side wall insulating film
109
of each N channel MOS transistor
111
a
and
111
b
and the contact plug
113
of the drain in order to partition the N
+
diffusion layer
104
b
into two regions. A silicide layer
106
is formed directly below the mask insulating film
118
. Accordingly, the silicide layer
106
formed on the N
+
diffusion layer
104
b
is partitioned into three regions.
In the second conventional example, since the resistance of the drain diffusion layer of each N channel MOS transistor
111
a
and
111
b
is higher than that of the first conventional example, the electrostatic resistance of the second embodiment is higher.
In addition, a semiconductor device, in which a high resistance region is formed between the drain diffusion layer of a MOS transistor constituting an output circuit and an output pin, has been disclosed (in U.S. Pat. No. 5,019,888). Hereinafter, this semiconductor device is referred to as called the third conventional example.
In the third conventional example, the high resistance region formed between the drain and the output pin blocks the surge current flowing into the semiconductor device, so that a higher electrostatic resistance that that of the first conventional example is obtained, similar to the second embodiment.
However, although it is possible to improve the electrostatic resistance in the second and third conventional example, a problem arises in the practical semiconductor devices. That is, in practical semiconductor devices, a plurality of transistors are formed in parallel in one well, and stress is concentrated on one transistor and the transistor subjected to the concentrated stress is more likely to be broken.
FIG. 46A
is a cross-sectional view showing the propagation path of an surge current in the first conventional example, and
FIG. 46B
is a diagram showing the change of the voltage applied to the drain diffusion layer due to the surge current. It is noted that the silicide film
106
is omitted.
When an ESD surge current flows into a pad
115
connected to the drain diffusion layer (the N
+
diffusion layer
104
b
), the drain voltage increases, and when the voltage reaches a certain voltage, an avalanche breakdown occurs at a PN junction between the drain diffusion layer (N
+
diffusion layer
104
b
) and the P-well
102
. In general, this voltage is called BVDS.
When the ESD surge current further increases, the breakdown current flows to the guard ring (P
+
diffusion layer
105
) through a parasitic resistor
116
and passes through the ground (GND). Thereby, the voltage of the P-well increases in the proximity of the source diffusion layer (N
+
diffusion layer
104
a
) according to the voltage drop due to the parasitic resistor
116
.
When the drain voltage reaches V
1
due to the further increase of the ESD surge current, the PN junction between the source diffusion layer ((N
+
diffusion layer
104
a
) and the P-well
102
is forward biased and the parasitic bipolar transistor
117
is turned on, and the N-channel MOS transistor
111
a
enters snapback. As a result, not only the breakdown current flow from the drain diffusion layer ((N
+
diffusion layer
104
b
) to the guard ring (P
+
diffusion layer
105
) but also, the snapback current flows from the drain diffusion layer (N
+
diffusion layer
104
b
) to the source diffusion layer ((N
+
diffusion layer
104
a
), and the drain voltage decreases to a certain voltage Vsnp.
Thereafter, if the ESD surge current further increases, the drain voltage increases, and when the drain voltage reaches a certain voltage Vmax, the N-channel MOS transistor
111
a
is destroyed due to the rise of the temperature.
Since the breakdown current fl
Hirata Morihisa
Kato Osamu
Morishita Yasuyuki
Choate Hall & Stewart
Flynn Nathan J.
NEC Electronics Corporation
Sefer Ahmad N.
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