Semiconductor device and method of manufacturing the same

Details Semiconductor device and method of manufacturing the same Semiconductor device and method of manufacturing the same

2000-10-27

2002-10-29

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Regenerative type switching device

Having at least four external electrodes

C257S107000

Reexamination Certificate

active

06472693

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to an improvement to reduce an ON voltage while sustaining a high breakdown voltage and ensuring a wide operating area.
BACKGROUND ART
FIG. 41
is a cross-sectional elevation of a conventional insulated gate bipolar transistor (hereinafter, referred to as “IGBT”) in the background art of the present invention. In this device
150
, as is in general in a power semiconductor device, a lot of unit cells UC connected in parallel are incorporated in a single semiconductor base body
93
in order to gain a large main current. The unit cells UC are minimum units constituting the device
150
and each has an IGBT structure, serving as an IGBT.
FIG. 41
shows one unit cell UC.
The device
150
has a structure of so-called “vertical-type” and “planar-type” IGBT. The “vertical-type” one has a structure in which a pair of main electrodes are connected to one and the other of two main surfaces of a semiconductor base body
93
and the “planar-type” one has a structure in which a gate electrode is opposed in parallel to one of the main surfaces of the semiconductor base body
93
. In the device
150
, the semiconductor base body
93
whose base material is a silicon comprises a p collector layer
81
and an n layer
82
. The n layer
82
comprises an n
+
buffer layer
95
having a junction between the p collector layer
81
and itself and an n
+
layer
83
exposed to an upper main surface of the semiconductor base body
93
. The p collector layer
81
is exposed to a lower main surface of the semiconductor base body
93
.
A p base layer
84
is selectively formed in a surface to which the n
−
layer
83
is exposed, and an n
+
emitter layer
85
is selectively formed in a surface to which the p base layer
84
is exposed. The n
+
emitter layer
85
is formed to be shallower than the p base layer
84
and inside the p base layer
84
. Further, the n
+
emitter layer
85
is divided into two regions in a single p base layer
84
. Therefore, a first region of the p base layer
84
sandwiched by the two divided regions of the n
+
emitter layer
85
and two second regions of the p base layer
84
sandwiched by the two divided regions and the n
−
layer
83
, respectively, are selectively exposed in the upper main surface of the semiconductor base body
93
.
An emitter electrode
89
is connected to the first region to which the p base layer
84
is exposed and part of a surface to which the n
+
emitter layer
85
is exposed in the upper main surface of the semiconductor base body
93
. Further, a gate insulating film
87
and a gate electrode
88
are formed on the second region of the p base layer
84
. Specifically, the gate electrode
88
is opposed to the second region of the p base layer
84
with the gate insulating film
87
sandwiched therebetween. As a result, the second region serves as a channel region CH. A collector electrode
94
is connected to the lower main surface of the semiconductor base body
93
, i.e., the surface to which the p collector layer
81
is exposed. The emitter electrode
89
and the collector electrode
94
serve as a pair of main electrodes.
When the device
150
is used, a power supply is connected (usually through a load) between the emitter electrode
89
and the collector electrode
94
. A collector voltage is thereby applied between the collector electrode
94
and the emitter electrode
89
so that a potential at the collector electrode
94
may become positive with the emitter electrode
89
as a reference. In this state, by controlling a voltage applied to the gate electrode
88
, i.e., a gate voltage with the emitter electrode
89
as a reference, the magnitude of a main current (collector current) flowing from the collector electrode
94
to the emitter electrode
89
can be controlled.
When a positive gate voltage higher than a gate threshold voltage inherent to the device
150
is applied, the channel region CH positioned immediately below the gate electrode
88
is inverted from natural p type to n type. Specifically, an n-type inversion layer is formed in the channel region CH. As a result, electrons flowing from the emitter electrode
89
through the n
+
emitter layer
85
is injected into the n
−
layer
83
through the channel region CH.
Since a portion between the p collector layer
81
and the n layer
82
(including the n
−
layer
83
and the n
+
buffer layer
95
) is biased in the forward direction by the implanted electrons, holes are injected from the p collector layer
81
into the n
−
layer
83
. That causes modulation of conductivity to largely reduce the resistance of the n
−
layer
83
, and therefore a large main current flows from the collector electrode
94
to the emitter electrode
89
. In other words, the device
150
is brought into conduction (an ON state).
Next, when the gate voltage is returned to zero or negative value, the channel region CH is returned to the natural p type. As a result, since the injection of the electrons from the emitter electrode
89
is stopped, the injection of the hole from the p collector layer
81
is also stopped. After that, the holes accumulated in the n
−
layer
83
(and the n
+
buffer layer
95
) are retrieved in the emitter electrode
89
and then extinguished. In other words, the device
150
is brought into a cut-off state (an OFF state).
Thus, the device
150
having the IGBT structure has an advantage that the collector voltage in the ON state, i.e., the ON voltage is low because the modulation of conductivity is used. In the IGBT, generally, the ON voltage V
CE
(SAT) is expressed by Eq. 1.
 
V
CE
(sat)=
V
MOS
+V
DIODE
  (Eq. 1)
where V
MOS
represents a voltage drop (ON voltage of a MOSFET) developed in a MOSFET equivalently constituted of the n
+
emitter layer
85
, the channel region CH and the n
−
layer
83
and V
DIODE
represents a voltage drop (ON voltage of a diode) developed in a diode equivalently constituted of the p collector layer
81
and the n layer
82
. As shown in Eq. 1, the ON voltage V
CE
(sat) can be divided into two components.
Further, when the IGBT is in the ON state, the resistance R of the n
−
layer
83
which causes the modulation of conductivity is expressed by Eq. 2.
R∝W
2/(
2
·{square root over ( )}(
D·&tgr;
2
))  (Eq. 2)
where W represents the thickness of the n
−
layer
83
, D represents a diffusion coefficient of the hole and &tgr; represents the lifetime of the hole in the n
−
layer
83
. As shown in Eq. 2, the resistance R of the n
−
layer
83
depends on the thickness W of the n
−
layer
83
and the lifetime &tgr;.
In order to achieve an IGBT of high breakdown voltage, it is necessary to set the thickness D of the n
−
layer
83
larger. For this reason, in the IGBT of high breakdown voltage, the ratio of the voltage drop V
DIODE
developed in the diode among the two components constituting the ON voltage V
CE
(sat) is high. In other words, in the IGBT of high breakdown voltage, reducing the ON voltage of the diode is more effective in reducing the ON voltage V
CE
(sat) than reducing the ON voltage of the MOSFET.
In this direction, as a semiconductor device with reduced On voltage V
CE
(sat), Kitagawa et al. proposes Injection Enhanced Transistor (IEGT) (“IEDM” (1993) pp. 679 to 682) and Takahashi et al. proposes Carrier Stored Trench-Gate bipolar Transistor (CSTBT) (“ISPSD” (1996) pp. 349 to 352). In the IEGT, part of a p base layer is not short circuited with an emitter electrode. That allows accumulation of a hole current injected from a p collector layer in an emitter region. As a result, since the carrier concentration near an emitter layer is increased and the modulation of conductivity is accelerated, the ON voltage V
DIODE
of a diode is improvingly lowered.
Further, in the CSTBT, an n
+
layer of relativel

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