Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame
Reexamination Certificate
2000-10-06
2002-08-27
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
Reexamination Certificate
active
06441472
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the structure of a multi-chip type semiconductor device in which a plurality of semiconductor chips are mounted, and a method for manufacturing it.
FIG. 11
is a sectional view of a conventional laminated multi-chip type semiconductor device disclosed in e.g. the Unexamined Japanese Patent Application Publication No. Hei 1-235363. In
FIG. 11
, reference numeral
101
a
denotes an upper semiconductor chip;
101
b
a lower semiconductor chip;
102
a tab;
103
an adhesive for pellet fixing such as an Ag paste;
104
a non-conductive adhesive for pellet fixing;
105
a
,
105
b
bonding wires;
106
a lead frame; and
107
resin for mold sealing.
FIG. 12
is a perspective view of a conventional laminated multi-chip type semiconductor device disclosed in e.g. the Japanese Patent Application Publication No. Hei 4-25166. In
FIG. 12
, reference numerals
111
a
,
111
b
denote a first and a second semiconductor chip;
112
a connecting electrode; and
113
a lead.
A detailed explanation will be given of the structure of the above semiconductor device.
In
FIG. 11
, the lower semiconductor chip
101
b
is pellet-fixed onto the tab
102
by the pellet-fixing adhesive
103
such as Ag paste. The upper semiconductor chip
101
a
is pellet-fixed onto the lower semiconductor chip
101
b
by the non-conductive adhesive for pellet-fixing
104
. Further, the upper and lower semiconductor chips
101
a
and
101
b
are connected to the lead frame
106
by the bonding wires
105
a
and
105
b
, respectively. These components are sealed by the mold sealing plastic
107
such as resin.
In
FIG. 12
, the semiconductor chips
111
a
and
111
b
have connecting electrodes
112
on the opposite two sides, respectively. These semiconductor chips
111
a
and
111
b
are arranged so that they are orthogonal to each other (i.e. the connecting electrodes
112
of the semiconductor chips
111
a
and
111
b
are not located on the same sides). These semiconductor chips
111
a
and
111
b
are fixedly superposed on each other by an adhesive. The connecting electrodes
112
are provided with leads
113
for electric connection.
The conventional laminated multi-chip type semiconductor device is structured as described above. Therefore, in the structure of
FIG. 11
, the upper semiconductor chip must be sufficiently smaller in size than the lower semiconductor chip. The semiconductor chips having equal sizes cannot be combined with each other.
Further, in the structure of
FIG. 12
, the connecting electrodes of the first and the second semiconductor chip must be arranged so that they are located on only two sides, respectively, and not located on the same sides as the other. In addition, combination of the upper and lower or first and second semiconductor chips must be carefully taken in consideration.
SUMMARY OF THE INVENTION
The present invention has been accomplished in order to solve the above problems, and intends to provide a laminated multi-chip type semiconductor device which is not required to consider the sizes of laminated semiconductor chips and the electrode arrangement in each semiconductor chip. The invention also intends to provide a method for manufacturing it.
The invention of the semiconductor device defined in claim
1
comprises: a first semiconductor chip with a front surface side (where a bonding electrode is located) bonded to a die-pad portion of a lead frame, and a second semiconductor chip with a rear surface bonded to the rear surface of the first semiconductor chip, and is characterized in that an electrode on the front surface of said first semiconductor chip and an inner lead portion of the lead frame are electrically connected to each other by a wire, and an electrode on the front surface of said second semiconductor chip and the inner lead portion are electrically connected to each other by the wire.
The invention of the semiconductor device defined in claim
2
is characterized in that said die-pad portion of the lead frame is divided into plurality portions and/or has a hole, and through the divided portion and/or the interior of the hole, the wire is electrically extended from the electrode of the first semiconductor chip to the inner lead portion of the lead frame.
The invention of the semiconductor device defined in claim
3
is characterized in that a plurality of first semiconductor chips are bonded to the die-pad portion of the lead frame.
The invention of the semiconductor device defined in claim
4
is characterized in that a plurality of the second semiconductor chips are bonded to said first semiconductor chip.
The invention of a method of manufacturing a semiconductor device defined in claim
1
comprises: a first die bonding step of bonding the front surface (where a bonding electrode is located) of a first semiconductor chip on a die-pad portion of a lead frame; a first wire bonding step of electrically connecting the electrode on the front surface of the first semiconductor chip to an inner lead portion of the lead frame by a wire; a second die bonding step of bonding rear surfaces of said first and said second semiconductor chip to each other; and a second wire bonding step of electrically connecting an electrode on the front surface of said second semiconductor chip to the inner lead portion of the lead frame by the wire.
The invention of a method of manufacturing a semiconductor device defined in claim
2
comprises a first die bonding step of bonding the front surface (where a bonding electrode is located) of a first semiconductor chip on a die-pad portion of a lead frame; a second die bonding step of bonding rear surfaces of said first and a second semiconductor chip to each other; a first wire bonding step of electrically connecting the electrode on the front surface of the first semiconductor chip to a inner lead portion of the lead frame by a wire; a second wire bonding step of electrically connecting an electrode on the front surface of said second semiconductor chip to the inner lead portion of the lead frame by a wire.
The invention of a method of manufacturing a semiconductor device defined in claim
3
comprises a first die bonding step of bonding the front surface (where a bonding electrode is located) of a first semiconductor chip on a die-pad portion of a lead frame; a second die bonding step of bonding rear surfaces of said first and a second semiconductor chip to each other; a second wire bonding step of electrically connecting an electrode on the front surface of said second semiconductor chip to an inner lead portion of the lead frame by a wire; and a first wire bonding step of electrically connecting the electrode on the front surface of the first semiconductor chip to the inner lead portion of the lead frame by the wire.
REFERENCES:
patent: 6118184 (2000-09-01), Ishio et al.
patent: 60-245291 (1985-12-01), None
patent: 4-25166 (1992-01-01), None
Hatauchi Kazushi
Mitarai Tadashi
Le Thao
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Nelms David
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