Semiconductor device and method of manufacturing the same

Details Semiconductor device and method of manufacturing the same Semiconductor device and method of manufacturing the same

2000-08-17

2002-12-17

Dang, Trung (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including dielectric isolation means

C257S509000, C257S510000, C438S405000, C438S410000, C438S425000, C438S427000

Reexamination Certificate

active

06495898

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, it relates to a semiconductor device including a MOS transistor having a gate oxide film prevented from dielectric breakdown and a method of manufacturing the same.
2. Description of the Background Art
A semiconductor device (hereinafter referred to as an SOI device) having an SOI (silicon on insulator) structure formed on an SOI substrate including a buried oxide film and an SOI layer arranged on a silicon substrate, which can reduce parasitic capacitance and operate at a high speed with lower power consumption, is employed for a portable device or the like.
FIG. 41
shows a partially fragmented sectional structure of an exemplary SOI device
70
electrically isolating MOS transistors by trench isolation.
Referring to
FIG. 41
, an SOI substrate includes a buried oxide film
2
and an SOI layer
3
arranged on a silicon substrate
1
, and an N-channel MOS transistor (NMOS transistor) N
1
and a P-channel MOS transistor (PMOS transistor) P
1
are arranged on the SOI layer
3
while an isolation oxide film
4
completely electrically isolates these MOS transistors N
1
and P
1
from each other. The isolation oxide film
4
is so arranged as to enclose the NMOS transistor N
1
and the PMOS transistor P
1
.
Each of the NMOS transistor N
1
and the PMOS transistor P
1
is formed by source/drain regions SD and a channel forming region CH formed in the SOI layer
3
, a gate oxide film GO formed on the channel forming region CH, a gate electrode GT formed on the gate oxide film GO and side wall oxide films SW covering the side surfaces of the gate electrode GT.
Thus, in the SOI device
70
, the NMOS transistor N
1
and the PMOS transistor P
1
are not only independent of each other in the SOI layer
3
due to the isolation oxide film
4
but also completely isolated from other semiconductor elements etc., whereby no latch-up takes place in principle in these transistors N
1
and P
1
.
When manufacturing an SOI device having a CMOS transistor, therefore, the minimum isolation width decided by a microlithography can be used and the chip area can be advantageously reduced. However, a substrate floating effect causes various problems such that carriers (holes in an NMOS transistor) generated by impact ionization are collected in the channel forming region to result in kinks or deteriorate an operating withstand voltage and such that instability of the potential of the channel forming region results in frequency dependency of a delay time.
In this regard, a partial trench isolation structure has been devised.
FIG. 42
is a partially fragmented sectional view showing an SOI device
80
having such a partial trench isolation structure (PTI structure).
Referring to
FIG. 42
, an NMOS transistor N
1
and a PMOS transistor P
1
are arranged on an SOI layer
3
while a partial isolation oxide film
5
having a well region WR arranged on its lower portion isolates the NMOS transistor N
1
and the PMOS transistor P
1
from each other. The partial isolation oxide film
5
is so arranged as to enclose the NMOS transistor N
1
and the PMOS transistor P
1
.
With respect to the partial isolation oxide film
5
, a structure such as that of the isolation oxide film
4
in the SOI device
70
completely electrically isolating elements with a trench oxide film reaching the buried oxide film
2
is referred to as a full trench isolation structure (FTI structure), and the oxide film is referred to as a full isolation oxide film.
While the partial isolation oxide film
5
isolates the NMOS transistor N
1
and the PMOS transistor P
1
from each other, carriers are movable through the well region WR on the lower portion of the partial isolation oxide film
5
and can be prevented from being collected in channel forming regions while the potential of the channel forming regions can be fixed through the well region WR, whereby no problems are caused by a substrate floating effect.
Whether an SOI device employs the PTI structure or the FTI structure, however, new manufacturing steps must be added for increasing the thickness of gate oxide films in order to improve reliability of MOS transistors and adjusting the quantity of an impurity injected into channels in order to reduce threshold voltages.
A method of manufacturing an SOI device
90
having a PTI structure improving reliability of MOS transistors is now described with reference to
FIGS. 43
to
50
.
First, an SOI substrate structured by a silicon substrate
1
, a buried oxide film
2
and an SOI layer
3
, formed by a SIMOX method forming the buried oxide film
2
by oxygen ion implantation or a bonding method is prepared. In general, the thickness of the SOI layer
3
is 50 to 200 nm, and the thickness of the buried oxide film
2
is 100 to 400 nm. As shown in
FIG. 43
, an oxide film
6
of about 10 to 30 nm (100 to 300 Å) in thickness is formed on the SOI substrate by CVD or thermal oxidation, and a nitride film
7
of 30 to 200 nm (300 to 2000 Å) in thickness is formed thereon. Then, a resist mask RM
1
is formed on the nitride film
7
by patterning. The resist mask RM
1
has an opening for forming a trench.
Then, the resist mask RM
1
is employed as a mask for patterning the nitride film
7
, the oxide film
6
and the SOI layer
3
by etching thereby forming a partial trench TR in the SOI layer
3
, as shown in FIG.
44
. In this etching, etching conditions are so adjusted as not to completely etch the SOI layer
3
and expose the buried oxide film
2
but to leave the SOI layer
3
on the bottom of the trench TR in a prescribed thickness.
The partial trench TR
1
is formed to extend substantially perpendicularly to the silicon substrate
1
with a prescribed width, whereby element isolation can be performed while maintaining refinement without deteriorating the degree of integration.
In a step shown in
FIG. 45
, an oxide film of about 500 nm (5000 Å) in thickness is deposited, a portion up to an intermediate portion of the nitride film
7
is polished by CMP (chemical mechanical polishing), and thereafter the nitride film
7
and the oxide film
6
are removed thereby forming a partial isolation oxide film
5
. It is assumed here that the region located on the left side of the partial isolation oxide film
5
in
FIG. 45
is a first region R
1
for forming a transistor having a low threshold voltage while the region located on the right side of the partial isolation oxide film
5
is a second region R
2
for forming a highly reliable transistor having a general threshold voltage.
In a step shown in
FIG. 46
, an oxide film OX
1
is formed on the overall area of the SOI layer
3
. The thickness of the oxide film OX
1
is 1 to 4 nm (10 to 40 Å). Thereafter a resist mask RM
2
is formed to cover the second region R
2
, and a semiconductor impurity is introduced into the SOI layer
3
of the first region R
1
by ion implantation through the oxide film OX
1
. As to the conditions for this implantation for forming the transistor having a low threshold voltage, boron (B) ions are implanted with energy of 5 to 40 keV and in a dose of 1×10
11
to 3×10
11
/cm
2
when forming an NMOS transistor, for example. In advance of this step, boron ions are implanted with energy of 30 to 100 keV and in a dose of 1×10
12
to 1×10
14
/cm
2
for forming a well region.
In a step shown in
FIG. 47
, a resist mask RM
3
is formed to cover the first region R
1
, and a semiconductor impurity is introduced into the SOI layer
3
of the second region R
2
by ion implantation through the oxide film OX
1
. As to the conditions for this implantation for forming the transistor having a general threshold voltage, boron (B) ions are implanted with energy of 5 to 40 keV and in a dose of 3×10
11
to 5×10
11
/cm
2
when forming an NMOS transistor, for example.
In a step shown in
FIG. 48
, a resist mask RM
4
is formed to cover the second region R
2
, and

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