Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip
Reexamination Certificate
2001-05-30
2002-12-03
Clark, Jasmine J B (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Chip mounted on chip
C257S685000, C257S686000, C257S723000
Reexamination Certificate
active
06489687
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a semiconductor device and a method of manufacturing the same, a manufacturing device, a circuit board, and electronic equipment.
BACKGROUND OF ART
Accompanied by miniaturization of electronic equipment, multichip modules including a plurality of semiconductor chips at high density have been developed. Since a plurality of existing semiconductor chips can be used in the multichip modules, cost can be reduced in comparison with the case of designing an original integrated circuit.
In the multichip modules, a plurality of semiconductor chips is mounted on the surface of a substrate on which an interconnecting pattern is formed and the substrate is bent to form a multilayer structure, for example. As multichip modules which can achieve miniaturization and an increase in density, semiconductor modules in which a plurality of semiconductor chips is mounted on both surfaces of the substrate and the substrate is bent are known. However, in such semiconductor modules, the interconnecting patterns must be formed on both surfaces of the substrate, and via-holes for allowing these interconnecting patterns to be electrically connected are needed, thereby increasing cost and the number of manufacturing steps.
DISCLOSURE OF INVENTION
The present invention has been achieved to solve this problem. An objective of the present invention is to provide a semiconductor device and a method of manufacturing the same which can achieve a miniaturized high-density multichip module, a manufacturing device, a circuit board, and electronic. equipment without decreasing productivity.
(1) A semiconductor device according to the present invention comprises:
at least one substrate including a plurality of holes formed therein and an interconnecting pattern provided to one surface of the substrate, part of the interconnecting pattern being formed so as to overlap with the holes,
at least one first semiconductor chip including a plurality of electrodes and provided to another surface of the substrate,
at least one second semiconductor chip including a plurality of electrodes and provided to the one surface of the substrate, and
a conductive member disposed in each of the holes for electrically connecting each of the electrodes of the first semiconductor chip to the interconnecting pattern.
In to the present invention, a plurality of semiconductor chips can be provided to both surfaces of the substrate with the interconnecting pattern provided to one surface. Therefore, cost and the number of mounting steps can be reduced in comparison with a substrate with the interconnecting patterns formed over both surfaces. Moreover, the weight of the semiconductor device can be reduced. Because of this, a multichip module excelling in productivity can be developed.
(2) In this semiconductor device, the first semiconductor chip and the second semiconductor chip may have sections overlapping each other in plane view.
This enables the planar area for mounting the semiconductor chips to be efficiently utilized.
(3) In this semiconductor device, the electrodes of at least one of the first semiconductor chip and the second semiconductor chip may be connected to the interconnecting pattern by wire bonding.
This enables the present invention to be applied by using a wire as the conductive member.
(4) In this semiconductor device, at least one of the first semiconductor chip and the second semiconductor chip may be bonded face down.
(5) In this semiconductor device, the first semiconductor chip and the second semiconductor chip may be bonded face down, and the electrodes of the first semiconductor chip may be disposed in the holes.
(6) In this semiconductor device, a resin may be provided between the substrate and the first semiconductor chip.
The resin has a function of reducing stress.
(7) In this semiconductor device, a resin may be provided between the substrate and the second semiconductor chip.
The resin can be provided on each semiconductor chip.
(8) In this semiconductor device, the resin may be an anisotropic conductive material including conductive particles.
(9) In this semiconductor device, a plurality of the substrates may be provided, and part of the interconnecting patterns of a pair of the substrates may be disposed facing each other for electrical connection between the interconnecting patterns.
This enables a semiconductor device comprising a plurality of substrates to be used, whereby a greater number of semiconductor chips can be positioned.
(10) In this semiconductor device, the substrate may be bent.
According to this semiconductor device, since each semiconductor chip is stacked through the substrate by bending the substrate, the planar area of the semiconductor device can be decreased.
(11) In this semiconductor device, a plurality of at least one of the first semiconductor chips and the second semiconductor chips may be provided, and the plurality of at least one of the first semiconductor chips and the second semiconductor chips may be stacked.
This enables the planar area of the semiconductor device to be decreased.
(12) In this semiconductor device, the conductive member may be a plurality of layered bumps.
The conductive member can be formed by layering the bumps.
(13) In this semiconductor device, the first semiconductor chip and the second semiconductor chip may have the same outer shape.
(14) In this semiconductor device, the second semiconductor chip may have a mirror-symmetrical circuit structure with the first semiconductor chip.
This enables each of a pair of the semiconductor chips having a mirror-symmetrical circuit structure to be connected to both sides of the interconnecting pattern.
(15) In this semiconductor device, the electrodes of the second semiconductor chip may be connected to the interconnecting pattern over the holes.
Specifically, the electrodes may be disposed on both side of the interconnecting pattern respectively at the direct opposite position from each other.
(16) In this semiconductor device, the electrodes of the second semiconductor chip may be connected to the interconnecting pattern at a position avoiding the holes.
This enables the first and second semiconductor chips having different electrode arrangement to be positioned, for example.
(17) In this semiconductor device, a plurality of external terminals electrically connected to the first and second semiconductor chips may be formed on the substrate in a region other than a region in which the semiconductor chips are formed.
(18) In this semiconductor device, a plurality of external terminals may be formed over the interconnecting patterns avoiding a region in which at least one of the first semiconductor chip and the second semiconductor chip is formed.
(19) In this semiconductor device, the external terminals may be formed on one of the pair of interconnecting patterns in a region in which part of the interconnecting patterns are connected to each other.
This enables electrical connection to be established through the external terminals formed in the same region in case that a plurality of substrates are provided.
(20) In this semiconductor device, a plurality of through-holes may be formed in the substrate, part of the interconnecting pattern may run over the through-holes, and the external terminals project through the through-holes to a surface of the substrate to which the first semiconductor chip may be provided.
(21) A circuit board according to the present invention is provided with the above semiconductor device.
(22) Electronic equipment .according to the present invention has the above semiconductor device.
(23) A method of manufacturing a semiconductor device according to the present invention comprises:
a step of mounting a first semiconductor chip over one surface of a substrate which includes a plurality of holes and an interconnecting pattern formed over another surface, part of the interconnecting pattern running over the holes; and
a step of positioning a second semiconductor chip on the other surface of the substrate over which the interconnecting p
Clark Jasmine J B
Oliff & Berridg,e PLC
Seiko Epson Corporation
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