Semiconductor device manufacturing: process – Making device or circuit responsive to nonelectrical signal – Responsive to electromagnetic radiation
Reexamination Certificate
2001-07-09
2002-08-06
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making device or circuit responsive to nonelectrical signal
Responsive to electromagnetic radiation
C438S081000, C438S029000
Reexamination Certificate
active
06429039
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device. More particularly, the invention relates to a semiconductor device comprising photo detectors each made of a PN junction diode, as well as to a method of manufacturing such a semiconductor device.
2. Description of the Background Art
As a solid state image sensor for use in video cameras, there exist conventional semiconductor devices using a PN junction diode as a photo detector.
FIG. 23
shows a diagram of an equivalent circuit corresponding to one pixel in such a semiconductor device. As shown in
FIG. 23
, the typical semiconductor device includes per pixel a PN junction diode
10
working as a photo diode, and a control transistor
12
connected serially to the PN junction diode
10
.
FIG. 24A
is a cross-sectional view of a partial structure corresponding to the equivalent circuit in FIG.
23
.
FIG. 24B
is a plan view of the partial structure corresponding to the equivalent circuit. The conventional semiconductor device comprises a silicon single crystal substrate
14
arranged for use as a P-type semiconductor (simply called the P-type substrate
14
hereunder although including P-type wells formed in an N-type wafer). A surface area of the P-type substrate
14
is divided into single-pixel regions by an isolation oxide film
16
.
The P-type substrate
14
is furnished with a gate oxide film
18
, a gate electrode
20
, and side walls
22
laterally surrounding these elements. On one side of the gate electrode
20
are an N-type region
24
arranged for use as an N-type semiconductor and a P-type region
26
arranged for use as a P-type semiconductor. The N-type region
24
is formed by implanting N-type impurities such as phosphorus (P) or arsenic (As) into the P-type substrate
14
at a predetermined angle relative to the latter, i.e., in such a manner that the N-type impurities reach apart immediately below the gate oxide film
18
. After the N-type region
24
is formed, the P-type region
26
is produced by implanting P-type impurities such as boron (B) into the P-type substrate
14
at right angles to the latter. Between the N-type region
24
and the P-type region
26
, a PN junction plane
28
is produced.
On the other side of the gate electrode
20
is an LDD (Lightly Doped Drain) structure N-type drain region
30
. The N-type drain region
30
is formed by implanting N-type impurities into the P-type substrate
14
in a well-known manner.
In the structure shown in
FIGS. 24A and 24B
, the N-type region
24
and P-type region
26
constitute a PN junction diode
10
that functions as a photo diode. The gate electrode
20
and N-type drain region
30
make up a control transistor
12
connected to the PN junction diode
10
. In operation, light
32
enters the P-type region
26
, generating a light signal carrier
34
in the N-type region
24
in a manner proportional to the amount of the incident light
32
. The light signal carrier
34
that developed in the N-type region
24
is transferred to the N-type drain region
30
when a predetermined driving voltage is fed to the gate electrode
20
.
In the conventional semiconductor device outlined above, an insufficient carrier path that may develop between the PN junction diode
10
and the control transistor
34
prevents the light signal carrier
34
from being adequately transferred from the PN junction diode
10
. The result is a so-called afterimage phenomenon. In the structure shown in
FIGS. 24A and 24B
, a portion formed in a partially submerged manner immediately under the gate oxide film
34
(called the submerged portion hereunder) in the N-type region
24
constitutes the carrier path connecting the PN junction diode
10
to the control transistor
12
. To forestall the afterimage phenomenon thus requires providing the submerged portion of the N-type region
24
with a sufficient carrier transfer capability.
In order to confer an adequate carrier transfer capability to the submerged portion of the N-type region
24
, it is necessary to implant N-type impurities of a high enough concentration underneath the gate oxide film
18
. More specifically, a partially submerged portion containing highly concentrated N-type impurities of a uniform distribution needs to be formed by implanting the impurities into the flat P-type substrate
14
at an angle with respect to the latter.
The trouble is that such a partially submerged portion meeting the above requirements is difficult to form through the use of conventional semiconductor device manufacturing techniques. As a result, conventional semiconductor devices tend to be lacking in the carrier transfer capability of the submerged portions in the N-type region
24
and are thus susceptible to the afterimage phenomenon.
Conventional semiconductor devices offer higher resolutions as the PN junction diode
10
shows a higher sensitivity. The sensitive of the PN junction diode
10
improves as the amount of light incident on the P-type region
26
becomes grater, the area of the PN junction plane
28
becomes wider, and the level of light-gathering efficiency of the P-type region
26
becomes higher.
Conventional semiconductor devices attain higher degrees of integration the narrower the area occupied by the P-type region
26
. One known way to enhance the sensitivity of the PN junction diode
10
without increasing the area occupied by the P-type region
26
is by furnishing individual P-type regions
26
with a convex microlens each. The convex microlens condenses diffused light and causes the condensed light to enter the P-type region
26
, boosting the sensitivity of the PN junction diode
10
. This is an effective technique for maintaining a high degree of integration while attaining a high level of resolution at the same time.
Except for the convex microlens technique, there are few other methods conventionally employed to enhance the sensitivity of the PN junction diode
10
without increasing the area taken up by the P-type region
26
. So far, there have not been many in-depth studies on how to enhance the light-gathering efficiency of the P-type region
26
without increasing the area occupied by the PN junction plane
28
.
SUMMARY OF THE INVENTION
It is therefore a first object of the present invention to overcome the above and other deficiencies of the prior art and to provide a semiconductor device including a carrier path having a sufficient carrier transfer capability between a PN junction diode and a control transistor, and a method of manufacturing such a semiconductor device.
It is a second object of the present invention to provide a semiconductor device having a wide effective area for a PN junction plane and comprising PN junction diodes offering enhanced light-gathering efficiency, as well as a method of manufacturing such a semiconductor device.
The above objects of the present invention are achieved by a semiconductor device described below. The device includes a PN junction diode and a control transistor. The PN junction diode functions as a photo diode and comprises a semiconductor of a first conduction type that is one of a P- and an N-type and another semiconductor of a second conduction type that is the other of the two types. The control transistor controls transfer of a light signal carrier generated within the PN junction diode. The semiconductor device also includes a first conduction type substrate adjusted for said first conduction type. A gate oxide film and a gate electrode are furnished on a surface of the first conduction type substrate. A concave portion is provided in a region of the first conduction type substrate, which region is contiguous to the gate electrode. A second conduction type drain region is disposed on the opposite side of the gate electrode from the concave portion. A second conduction type region which includes a region underneath the concave portion is provided in the first conduction type substrate in a partially submerged manner underneath
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Niebling John F.
Simkovic Viktor
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