Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2011-05-17
2011-05-17
Luu, Chuong A. (Department: 2892)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S780000, C257S784000, C257S787000
Reexamination Certificate
active
07944039
ABSTRACT:
A semiconductor device includes a chip, a laminated wiring structure formed integrally with the chip, a frame disposed to surround the chip and made of a material having stiffness, and a sealing resin formed to bury therein the frame and at least the periphery of the side surface of the chip. The laminated wiring structure includes a required number of wiring layers, which are formed by patterning in such a manner that a wiring pattern directly routed from an electrode terminal of the chip is electrically connected to pad portions for bonding external connection terminals, the pad portions being provided, at a position directly below a mounting area of the chip and at a position directly below an area outside the mounting area, on a surface to which the external connection terminals are bonded.
REFERENCES:
patent: 5969426 (1999-10-01), Baba et al.
patent: 6071755 (2000-06-01), Baba
patent: 6317333 (2001-11-01), Baba
patent: 6879034 (2005-04-01), Yang et al.
patent: 6952049 (2005-10-01), Ogawa et al.
patent: 8-167629 (1996-06-01), None
“Bumpless Build-Up Layer Packaging” / The related part: Figure 1 ASME International Mechanical Engineering Congress and Exposition (IMECE) (Nov. 11, 2001).
Kratz Quintos & Hanson, LLP
Luu Chuong A.
Shinko Electric Industries Co. Ltd.
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