Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material
Reexamination Certificate
2000-05-02
2001-10-09
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
C438S682000, C438S199000, C438S271000, C257S369000, C257S393000
Reexamination Certificate
active
06300229
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same. More particularly, the present invention relates to a complementary metal oxide semiconductor (CMOS) device and a method of manufacturing thereof.
2. Description of Related Art
As the integration scale of semiconductor integrated circuit design has increased, it has become common practice to provide a large-scale integrated circuit (LSI) which contains a high-speed logic circuit and a large-capacity memory on a single semiconductor chip. For achieving higher speed in semiconductor integrated circuit operation, it is desirable to increase the degree of integration by arranging MOS transistors in a finer structure. For higher integration, an increase in wiring density, i.e., a decrease in average wiring length is also preferable.
In particular, a CMOS cell using six transistors has a relatively large margin of operation and a relatively small current for data retention, and therefore is contained in most CMOS SRAMs at present. However, since the memory cell area of the CMOS SRAM cell is rather large, there is a need to reduce the cell area for improvement in device integration.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a CMOS device which has higher wiring density for increasing the degree of integration, and a method of manufacturing the same.
According to one aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising the steps (a) to (h):
(a) forming an active region and an element isolation region in predetermined areas of a semiconductor substrate;
(b) forming first, second and third wiring layers on the active region and element isolation region with a dielectric layer interposed,
the first wiring layer connecting a gate electrode of a first load transistor with a gate electrode of a first drive transistor,
the second wiring layer connecting a gate transistor of a second load transistor with a gate transistor of a second drive transistor, and
the third wiring layer connecting the first wiring layer with an impurity diffusion layer of the second drive transistor;
(c) forming first, second and third cover dielectric layers that continuously cover side and top surfaces of the first, second and third wiring layers, respectively;
(d) forming a first impurity diffusion layer of a first conductive type and a second impurity diffusion layer of a second conductive type in the active region; and
forming a third impurity diffusion layer of the first conductive type and a fourth impurity diffusion layer of the second conductive type in the active region;
(e) self-alignably forming a first local wiring layer for connecting the first impurity diffusion layer with the second wiring layer; and
self-alignably forming a second local wiring layer for connecting the fourth impurity diffusion layer with the third wiring layer;
(f) forming an interlayer dielectric layer;
(g) self-alignably forming a first contact hole on the semiconductor substrate in a predetermined area of the interlayer dielectric layer by using at least the first and third cover dielectric layers as masking layers to expose a part of each of the first impurity diffusion layer, the third cover dielectric layer, the element isolation region and the second impurity diffusion layer; and
self-alignably forming a second contact hole on the semiconductor substrate in a predetermined area of the interlayer dielectric layer by using at least the second cover dielectric layer as a masking layer to expose a part of each of the third impurity diffusion layer, the element isolation region and the fourth impurity diffusion region; and
(h) forming a fourth wiring layer in the first contact hole, and a fifth wiring layer in the second contact hole.
At the step (g), the first contact hole can be selfalignably formed in the interlayer dielectric layer (first layer) by using at least the first cover dielectric layer for covering the first wiring layer and the third cover dielectric layer for covering the third wiring layer to provide masking, and the second contact hole can also be formed self-alignably in the interlayer dielectric layer by using at least the second cover dielectric layer to provide masking. Therefore, in a lithographic process in which contact holes are formed, it is not required to take account of an alignment error, leading to improvement in wiring density.
At the step (e), the first impurity diffusion layer and the second wiring layer are connected by means of the first local wiring layer that is self-alignably formed without using a contact hole, and the fourth impurity diffusion layer and the third wiring layer are connected by means of the second local wiring layer that is self-alignably formed. In this respect, a degree of device integration can also be improved.
In this method of manufacturing a semiconductor device, the first, second, and third wiring layers formed at the step (b) may contain silicon. These wiring layers may have a doped polysilicon single-layer structure or a polycide structure in which a doped polysilicon layer and a silicide layer are laminated.
The local wiring layer is preferably provided as a metallic silicide layer formed by a salicide (self-alignedsilicide) processing technique. More specifically, the first local wiring layer may comprise a metallic silicide layer which is formed by removing a part of the second cover dielectric layer to expose a part of the second wiring layer and then by self-aligning with the exposed surfaces of the first impurity diffusion layer and the second wiring layer. The second local wiring layer may comprise a metallic silicide layer which is formed by removing a part of the third cover dielectric layer to expose a part of the third wiring layer and then by self-aligning with the exposed surfaces of the fourth impurity diffusion layer and the third wiring layer.
According to another aspect of the present invention, there is provided a semiconductor device which comprises a memory cell including first and second load transistors, first and second drive transistors and two transfer transistors, the semiconductor device comprising:
a first wiring layer for connecting a gate electrode of the first load transistor with a gate electrode of the first drive transistor, formed on an active region and an element isolation region, with a dielectric layer interposed;
a first cover dielectric layer for continuously covering side and top surfaces of the first wiring layer;
a first impurity diffusion layer of a first conductive type that is a part of the first load transistor, and a second impurity diffusion layer of a second conductive type that is a part of the first drive transistor, both of which are formed in an active region;
a second wiring layer for connecting a gate electrode of the second load transistor with a gate electrode of the second drive transistor, formed on the active region and element isolation region, with a dielectric layer interposed, apart from the first wiring layer;
a second cover dielectric layer for continuously covering side and top surfaces of the second wiring layer;
a third impurity diffusion layer of the first conductive type that is a part of the second load transistor, and a fourth impurity diffusion layer of the second conductive type that is a part of the second drive transistor, both of which are formed in an active region;
a third wiring layer for connecting the first wiring layer with the fourth impurity diffusion layer, at least a part of the third wiring layer being disposed on the element isolation region;
a third cover dielectric layer for continuously covering side and top surfaces of the third wiring layer;
a first local wiring layer for connecting the first impurity diffusion layer with the second wiring layer;
a second local wiring layer for connecting the fourth impurity diffusion layer with the third wiring layer;
an interlayer dielectric layer including:
a first contact hole which ex
Karasawa Junichi
Kumagai Takashi
Tanaka Kazuo
Watanabe Kunio
Hogan & Hartson L.L.P.
Seiko Epson Corporation
Smith Matthew
Yevsikov V.
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