Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Having substrate registration feature
Reexamination Certificate
1998-11-27
2001-04-17
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Having substrate registration feature
C438S430000, C438S592000, C438S975000
Reexamination Certificate
active
06218262
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to an alignment mark for accurately aligning an element activation region to a first electrode.
2. Description of the Background Art
During production of a semiconductor integrated circuit, in order to control individual elements completely independently from each other by eliminating electric interference between the elements when the elements operate, it is necessary to form an element isolation structure which includes an element isolation region. As an element isolation method, trench-type element isolation has been proposed which requires to form a trench in a semiconductor substrate and bury an insulation film in the trench.
In the following, a conventional trench-type element isolation structure and a method of manufacturing the same will be described.
FIG. 40
shows a cross sectional structure of a DRAM as it is after a trench-type element isolation structure is formed. Trenches
10
A to
10
C are formed within a silicon substrate
1
. More precisely, the trench
10
B which has a narrow width is formed in a memory cell area
11
B, and the trenches
10
A and
10
C which are wider than the trench
10
B are formed respectively in an alignment mark area
11
A and a peripheral circuit area
11
C. Silicon oxide films
2
A to
2
C are buried in the trenches
10
A to
10
C.
The height of a surface of the silicon oxide film
2
within the trenches is approximately the same as the height of a surface of the silicon substrate
1
except for the silicon oxide film
2
. As a result, the surface of the silicon substrate
1
is approximately flat.
FIGS. 41
to
47
are cross sectional views showing a method of manufacturing the DRAM which has such a structure which is shown in FIG.
40
. Now, the manufacturing method will be described with reference to
FIGS. 41
to
47
.
First, after forming a silicon oxide film
3
and a silicon nitride film
4
in this order on the silicon substrate
1
, the silicon nitride film
4
and the silicon oxide film
3
in a predetermined region are removed using a photolithographic technology and a dry etching technology, thereby forming a trench
10
(
10
A to
10
C) of a predetermined depth in the silicon substrate
1
. That is, the relatively wide trench
10
A is formed in the alignment mark area
11
A, the relatively narrow trench
10
B is formed in the memory cell area
11
B, and the relatively wide trench
10
C is formed in the peripheral circuit area
11
C.
Following this, as shown in
FIG. 42
, after thermally oxidizing side surfaces and bottom surfaces of the trenches
10
, the silicon oxide film
2
is deposited by the LP-CVD (low pressure CVD) method. At this stage, since the silicon oxide film
2
is buried in the relatively narrow trench
10
B during an initial stage of the deposition while the silicon oxide film
2
is deposited into a film thickness which is equal to the deposited film thickness within the relatively wide trenches
10
A and
10
C, a film thickness of the silicon oxide film
2
as viewed from the bottom of the trench
10
B is thicker than the film thickness of the silicon oxide film
2
within the alignment mark area
11
A and the peripheral circuit area
11
C. That is, the silicon oxide film
2
which is deposited on the trench
10
B is different in film thickness from the silicon oxide film
2
which is deposited on the trenches
10
A and
10
C. In the following, the difference will be referred to as an on-the-trench silicon oxide film thickness difference.
Next, as shown in
FIG. 43
, to reduce the on-the-trench silicon oxide film thickness difference, a resist pattern
5
is formed only on the silicon oxide film
2
where the width of the silicon oxide film
2
is wide, using a photolithographic technology. The silicon oxide film
2
is thereafter partially removed by dry etching.
Following this, after removing the resist pattern
5
, the entire surface is polished by the CMP (Chemical Mechanical Polishing) method, thereby removing the silicon oxide film
2
on the silicon nitride film
4
and partially removing the silicon oxide film
2
within the trenches
10
A to
10
C. Next, as shown in
FIG. 44
, the silicon nitride film
4
is removed using phosphoric acid and the silicon oxide film
3
is removed using hydrofluoric acid, so that the buried silicon oxide film
2
A is formed within the alignment mark area
11
A, the buried silicon oxide film
2
B is formed within the memory cell area
11
B, the buried silicon oxide film
2
C is formed within the peripheral circuit area
11
C, thereby completing a trench-type element isolation structure.
Following this, as shown in
FIG. 45
, a gate oxide film
6
is formed by thermal oxidation, and a polysilicon film
7
and a tungsten silicide film
8
which are doped with phosphorus are deposited in this order on the gate oxide film
6
.
Next, as shown in
FIG. 46
, using the buried silicon oxide film
2
A (i.e., alignment mark) formed within the alignment mark area
11
A at the element isolation step, by a photolithographic technology, a resist pattern
9
is formed which aligns a gate electrode to an element isolation region.
As shown in
FIG. 47
, the tungsten silicide film
8
and the polysilicon film
7
are removed by dry etching using the resist pattern
9
as a mask, whereby a gate electrode portion
14
(
14
B to
14
D) is formed in the memory cell area
11
B and the peripheral circuit area
11
C. The gate electrode portion
14
D is used for alignment during formation of a contact hole to an active region which will be formed at a later step.
The conventional semiconductor device (DRAM) and the method of manufacturing the same described above have the following problems.
During patterning of the gate electrode portion
14
which is a first electrode material, in order to form a pattern in a predetermined area of the active region, it is necessary to align the gate electrode portion
14
to the active region. For alignment, an alignment mark
2
A of the alignment mark area
11
A which is formed at the element isolation step is used.
Alignment methods are generally classified into a first method which recognizes a mark by means of detection of diffraction light which does not photosensitize a resist and a second method which recognizes image information. In the first method which detects a mark using diffraction light, a surface of a semiconductor substrate must includes a step portion which is created by a mark which is formed on the semiconductor substrate. In the second which detects by means of image recognition, a gate electrode material must transmit light so that mark information underneath is detected or a step portion formed at a surface must allow recognition of the mark information.
However, in a conventional semiconductor device which includes trench-type element isolation, since an alignment mark portion creates almost no step portion, detection of the mark is difficult with the first method which utilizes a stepped surface. Meanwhile, since a silicide film, which is contained as a gate electrode material, does not transmit light, detection of the mark is difficult also with the second method which utilizes image recognition.
As a result, a mark detect signal has a small S/N ratio which deteriorates an alignment accuracy, so that it is not possible to perform alignment during formation of a gate electrode.
If the buried silicon oxide film
2
A is formed lower than the surface of the substrate to solve such a problem, the alignment accuracy is improved. However, this causes that the surfaces of the buried silicon oxide films
2
B and
2
C of an element formation region (i.e., the memory cell area
11
B and the peripheral circuit area
11
C), which is formed simultaneously with the buried silicon oxide film
2
A, to be lower than the surface of the substrate.
This in turn concentrates electric fields from the gate electrode, so that a hump appears in a current/voltage characteristic of a
Horita Katsuyuki
Kuroi Takashi
Sakai Maiko
Sayama Hirokazu
Abbott Barbara E.
Fourson George
Mitsubishi Denki & Kabushiki Kaisha
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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