Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Field effect device in non-single crystal – or...
Reexamination Certificate
1999-03-18
2001-08-21
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Field effect device in non-single crystal, or...
C257S072000, C257S351000
Reexamination Certificate
active
06278132
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device using a crystalline semiconductor (inclusive of a single crystal and a non-single crystal) formed on an insulating substrate such as a glass substrate, quartz substrate, silicon wafer, and the like, and to a method of manufacturing the same. More particularly, it relates to a case of constructing a CMOS circuit by using a n-channel type and a p-channel type semiconductor device in a complementary combination.
2. Description of the Prior Art
Recently, a technique for manufacturing a thin film transistor (TFT) on an inexpensive glass substrate is rapidly advancing. This rapid progress is cause of the growing demand on active matrix display devices. A display device of an active matrix(-addressing) type comprises pixels in a matrix-like arrangement, and a TFT (pixel TFT) is provided to each of the pixels to control the data signal individually by using the switching function of each of the pixel TFTs.
The gate signals and data signals sent to the pixel TFTs thus provided in a matrix-like arrangement are controlled by the peripheral drive circuit formed on the same substrate. A generally prevailed technique for manufacturing a CMOS circuit, i.e., a circuit in which a n-channel TFT and a p-channel TFT are combined in a complementary arrangement, is employed in constructing such a control circuit.
Further, in constructing the peripheral drive circuit described above, a circuit TFT capable of high speed operation is required. Accordingly, a crystalline silicon film is mainly used for the active layer. Because a carrier in a crystalline silicon film moves more rapidly than in an amorphous silicon film, a TFT having superior electric characteristics can be implemented by using the crystalline silicon film.
In this case,
FIG. 1A
is the cross sectional view of an example of a CMOS circuit constructed from top-gate type TFTs. Referring to
FIG. 1A
, a base film
102
is formed on the surface of a glass or quartz substrate
101
. The structure also comprises a crystalline silicon film for an active layer
103
for a N-channel TFT, as well as another crystalline silicon film for an active layer
104
for a P-channel TFT.
The active layers described above are covered by a gate insulating film
105
, and gate electrodes
106
and
107
are formed thereon. The gate electrodes
106
and
107
are further covered by an interlayer insulating film
108
which electrically insulates the gate electrode from the take out line.
Further, source electrodes
109
and
110
as well as a drain electrode
111
, which are electrically connected to the active layers
103
and
104
via contact holes, are provided on the interlayer insulating film
108
. Because the present case refers to a CMOS circuit, the drain electrode
111
is common for the n-channel TFT and the p-channel TFT. Finally, the source and the drain electrodes
109
to
111
are covered by a protective film
112
to provide a CMOS circuit as shown in FIG.
1
A.
The structure shown in
FIG. 1A
is the simplest constitution of a CMOS circuit, and is an inverter which functions as a circuit for reversing the polarity of a signal. NAND circuit, NOR circuit, and far more complicated logic circuits can be realized by combining such simple CMOS circuits. Various types of electric circuits are designed in this manner.
However, as disclosed in Japanese Laid-open Patent Application No. 4-206971 and Japanese Laid-open Patent Application No. 4-286339, the CMOS circuits manufactured by using a crystalline silicon film suffered a problem that the electric characteristics of the n-channel TFT tend to shift in the direction of depletion, whereas that of the p-channel TFT tend to shift in the direction of enhancement.
The electric characteristics (Id-Vg characteristics) of the TFT in the above case is shown in FIG.
1
B. In
FIG. 1B
, the abscissa (Vg) shows the gate voltage, and the ordinate (Id) shows the drain current. The curve indicated by
113
shows the Id-Vg characteristics of the n-channel TFT, and that indicated by
114
shows the Id-Vg characteristics of the p-channel TFT.
The fact that the Id-Vg characteristics
113
of the n-channel TFT shift to the direction of depletion and that the Id-Vg characteristics
114
of the p-channel TFT shift to the direction of enhancement both signify that, as shown in
FIG. 1B
, they are deviated to the negative side with respect to the gate voltage Vg.
Thus, it can be seen that the Id-Vg characteristics
113
and
114
of the n-channel and p-channel TFTs are asymmetrical with respect to the gate voltage of 0 V, and the absolute value of the threshold voltage of the n-channel TFT and that of the p-channel TFT become greatly differed from each other.
However, as disclosed in Japanese Laid Open Patent application No. 4-206971, a deviation in the output voltage due to the difference in the threshold voltage (drive voltage) of the n-channel TFT and that of the p-channel TFT is the cause of decreasing operation speed or malfunction of the CMOS circuit.
To overcome the above problems, the references described above disclose a method of controlling the threshold voltage by adding an impurity element to impart single conductivity to the channel region of the TFTs.
Still, however, in the technique described above (referred to hereinafter as “channel doping”), the control of the quantity of addition was found difficult with decreasing quantity to a trace amount. To the experimental knowledge of the present inventors, no change in threshold value was observed to a quantity of addition of about 1×10
18
/cm
3
, but upon exceeding the value, an abrupt change in threshold value was observed for a minute change in concentration.
For instance, in case the shift to be controlled in the threshold voltage is 1 V or lower, a shift in the order of several tenths of volts is realized by an extremely small amount of addition.
Thus, to control the threshold value with high precision, it was found indispensable to precisely control the concentration of the impurity element. However, the delicate control of the impurity element is technically very difficult. For instance, according to the experimental experience of the present inventors, no change in threshold value was observed to a quantity of addition of about 1×10
18
/cm
3
, but upon exceeding the value, an abrupt change in threshold value was observed for a minute change in concentration.
SUMMARY OF THE INVENTION
The present invention disclosed in the specification has been accomplished in the light of the aforementioned problems. It is therefore an object of the present invention to provide a technique to delicately control the threshold voltage by precisely controlling the concentration of the added impurity elements.
According to the present invention, a semiconductor device having a CMOS structure is characterized by comprising: an n-channel semiconductor device; a p-channel semiconductor device which is complementarily combined with said n-channel semiconductor device to form said CMOS structure; and a substrate having an insulating surface on which said n-channel semiconductor device and said p-channel semiconductor device are formed; wherein said p-channel semiconductor device has an active layer, only to which impurity elements that impart p-type conduction are intentionally added in a partial region of said active layer which includes at least a channel formation region; wherein the distribution of concentration of said impurity elements depthwise is continuously reduced toward a main surface of said active layer in the vicinity of the main surface of said active layer; and wherein said impurity elements remaining in the vicinity of the main surface of said active layer is used to control a threshold value voltage.
In the present invention, the concentration of the impurity ions for imparting p-type conductivity (representatively boron (B) ions) in the surface of the active layer (the surface on which the reverse layer is to be formed) is lowered by taki
Fukunaga Takeshi
Ohtani Hisashi
Yamazaki Shunpei
Eckert II George C.
Fish & Richardson P.C.
Lee Eddie
Semiconductor Energy Laboratory Co,. Ltd.
LandOfFree
Semiconductor device and method of manufacturing the same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device and method of manufacturing the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and method of manufacturing the same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2478034