Active solid-state devices (e.g. – transistors – solid-state diode – With means to control surface effects – Insulating coating
Reexamination Certificate
1999-07-26
2001-04-24
Lam, Cathy (Department: 1775)
Active solid-state devices (e.g., transistors, solid-state diode
With means to control surface effects
Insulating coating
C257S637000, C257S649000
Reexamination Certificate
active
06222256
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device comprising an interlayer isolation film isolating an upper layer wire and a lower layer wire interconnected through a contact hole and a method of manufacturing the same.
2. Description of the Background
In order to implement speed increase of a logic device following the subquarter micron generation, it is important to reduce signal delay of the device. While the signal delay of the device is expressed in the sum of delays in transistors and those in wires, influence by the signal delay in the wire increasingly exceeds that in the transistor following reduction of the wiring pitch. In order to reduce the signal delay in the wire, which is proportionate to the product of the resistance of the wire and the capacitance of an interlayer isolation film, either the wiring resistance or the capacitance of the interlayer isolation film must be reduced. As one of attempts for attaining this object, an interlayer isolation film having a low dielectric constant is actively studied.
In particular, a silicon oxide film containing fluorine (hereinafter referred to as F) is watched with interest. The relative dielectric constant of the silicon oxide film is reduced when bonds (hereinafter referred to as Si—F bonds) of silicon atoms and F atoms are introduced into the same. For example, the relative dielectric constant of 4.4 with no presence of Si—F bonds is reduced to 3.5 when F is introduced to be about 10% in atomic percentage concentration (a silicon oxide film containing F is hereinafter referred to as an SiOF film).
FIG. 16
typically illustrates the structure of a conventional semiconductor device D
3
employing an SiOF film as an interlayer isolation film. The semiconductor device D
3
comprises a base layer
101
including a substrate, elements formed on the substrate and an insulator layer formed to cover the substrate and the elements, and first layer metal wires
102
are selectively formed on a surface of the base layer
101
(in order to avoid complicated illustration,
FIG. 16
shows neither the substrate, the elements and the insulator layer of the base layer
101
nor some of the first layer metal wires
102
connected with the elements of the base layer
102
). The semiconductor device D
3
further comprises an SiOF film
103
sufficiently covering the first layer metal wires
102
on the surfaces of the first layer metal wires
102
, and a spacer film
104
consisting of a silicon oxide film, for example, having a flat surface is formed on a surface of the SiOF film
103
. Second metal wires
105
of an Al alloy, for example, are selectively formed on the surface of the spacer film
104
(although not illustrated, the first and second layer metal wires
102
and
105
are generally in a multilayer structure of a barrier metal prepared by stacking TiN and Ti and a wiring metal such as an Al alloy).
In this semiconductor device D
3
, the SiOF film
103
and the spacer film
104
combinedly serve as an interlayer isolation film between the first layer metal wires
102
and the second layer metal wires
105
. Due to the presence of the SiOF film
103
, the electrostatic capacitance between the first layer metal wires
102
and the second layer metal wires
105
is at a smaller value than that through an interlayer isolation film consisting of only a silicon oxide film containing no F, for example.
FIGS. 17
to
20
successively show steps in a method of manufacturing the semiconductor device D
3
. First, the elements are formed on the substrate and then the insulator layer is formed to cover the substrate and the elements, thereby preparing the base layer
101
. Then, a metal film for the barrier metal and a metal film for the wires are formed on the surface of the base layer
101
and worked into a prescribed pattern by photolithography, for forming the first layer metal wires
102
(FIG.
17
). Then, the SiOF film
103
is formed to cover the first layer metal wires
102
. At this time, the SiOF film
103
is formed by high density plasma CVD (hereinafter referred to as HDPCVD) to sufficiently fill up clearances between the adjacent first layer metal wires
102
.
Then, a silicon oxide film is formed as the spacer film
104
on the surface of the SiOF film
103
by plasma CVD, for example (FIG.
18
). Then, an irregular surface of the spacer film
104
is polished by chemical mechanical polishing (hereinafter referred to as CMP), thereby forming a flat surface
104
A (FIG.
19
). Then, a metal film is formed on the flat surface
104
A similarly to that for the first layer metal wires
102
, for forming the second layer metal wires
105
by photolithography (FIG.
19
).
The reason for preparing the interlayer isolation film not only from the SiOF film
103
but also from the spacer film
104
is now described. When its surface is exposed to an atmosphere containing moisture, an SiOF film having low density readily absorbs the moisture contained in the atmosphere. Molecules of water, which are slightly polarized even in an ordinary state, disadvantageously raise the relative dielectric constant of the SiOF film when taken into the film. If no spacer film
104
is formed on the SiOF film
103
of the semiconductor device D
3
, the SiOF film
103
must be flattened by CMP. This is because formation of upper wires or the interlayer isolation film may be hindered if the interlayer isolation film is irregular. In CMP, however, water is splashed on the surface of the semiconductor device D
3
in the stage of polishing or posttreatment, and hence the SiOF film
103
remarkably absorbs water. Then, it follows that the relative dielectric constant of the SiOF film
103
, which must have a low dielectric constant, increases. In order to avoid such a situation, therefore, the spacer film
104
must be formed on the surface of the SiOF film
103
as a spacer for CMP.
In order to reduce the relative dielectric constant of the SiOF film, the concentration of F contained therein may be increased. If the concentration of F is excessively increased, however, instable F insufficiently bonded with Si comes to exist in the film. In this case, the instable F desorbs from the Si—F bonds in the stage of heat treatment after film formation and diffuses in the interlayer isolation film, to reach the metal wires formed on the interlayer isolation film. While the metal wires are generally formed by stacking an Al alloy or the like on a barrier metal prepared by stacking TiN and Ti as described above, F reaching the metal wires react with Ti contained in the barrier metal to form a titanium fluoride. This titanium fluoride has extremely inferior adhesion to the interlayer isolation film, and hence the barrier metal readily peels off on the interface between the same and the interlayer isolation film due to influence by stress occurring in the later step of CMP or the like.
FIGS. 21A
to
21
C illustrate this problem with reference to a region RG in FIG.
16
.
FIG. 21A
shows the second layer metal wire
105
as a multilayer structure of a wiring metal
105
a
and a barrier metal
105
b.
When instable F atoms
108
contained in the SiOF film
103
move toward the outermost surface side of the spacer film
104
through the heat treatment in the later step as shown in
FIG. 21B
, a layer
105
c
of a titanium fluoride is formed in the barrier metal
105
b
as shown in FIG.
21
C.
FIG. 22
shows distribution of the respective components forming the region RG along the film thickness direction through SIMS (secondary ion mass spectroscopy). Referring to
FIG. 22
, the F distribution has its maximum P in the Ti layer, to prove that F diffuses from the SiOF film
103
and reacts with the Ti layer in the barrier metal
105
b
to form the titanium fluoride.
Thus, a countermeasure is necessary for preventing F contained in the SiOF film from diffusing into the metal wires while increasing the F concentration in the film. A technique of forming a film (hereinafter referred to as an F diffusion prevention
Goto Kinya
Matsuura Masazumi
Lam Cathy
Mitsubishi Denki & Kabushiki Kaisha
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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