Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
1998-01-13
2001-04-17
Everhart, Caridad (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C438S132000, C438S662000
Reexamination Certificate
active
06218721
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device which has a fuse and is used for replacement of a redundant cell or the like, and a method of manufacturing the same.
In recent years, the degree of integration of semiconductor devices increases more and more, and accordingly the manufacturing yield generally tends to decrease. In particular, in a recent semiconductor memory device, several extra redundant bit cells are included in a memory cell array to replace a defective bit cell. Therefore, even if a defective bit cell is generated, the chip that includes this defective bit cell need not be determined as a defective chip, so that a decrease in yield is prevented.
To replace the defective bit cell with the redundant bit cell, as will be described later, a fuse interconnection which has been made in advance is fusion-disconnected by a laser or the like, and the circuit connection is altered.
For example,
FIG. 8
shows a circuit diagram including a redundant circuit which saves a defective memory cell with a preliminary redundant memory cell. Reference numeral
801
denotes a power supply Vcc;
802
, a GND;
803
and
809
, capacitors;
804
and
810
, fuses;
805
,
806
,
807
,
811
,
812
, and
817
, inverter circuits;
808
a
, a redundant line selection circuit;
813
, an XOR circuit;
814
a
and
814
b
, address selection circuits;
815
, a NAND circuit as the decoder of the redundant line;
816
, a signal for disabling a regular decoder; and
818
, a redundant line.
The operation of the redundant circuit shown in
FIG. 8
will be described. In a normal operation in which the redundant circuit is not used, the fuse
804
is grounded to the GND
802
. Accordingly, a low “L” level signal is input to the inverter circuit
805
. The output of the inverter circuit
805
changes to high “H” level and input to the next-stage inverter circuit
807
. The inverter circuit
806
latches an “H” level signal.
A signal re output from the inverter circuit
807
changes to “L” level, and the output
816
of the NAND circuit
815
is constantly at “H” level. The redundant line
818
is inverted by the inverter circuit
817
to be constantly at “L” level. Therefore, the redundant line
818
is in a non-selected state.
When the redundant line is used, the fuse
804
in the redundant line selection circuit
808
a
is disconnected, and simultaneously the fuses
810
in the address selection circuits
814
a
and
814
b
corresponding to a defective address are also disconnected as required.
Since the fuse
804
in the redundant line selection circuit
808
a
is disconnected as described above, an “H” level signal is input from the capacitor
803
connected to the power supply Vcc
801
to the inverter circuit
805
. As a result, the signal re changes to “H” level, and selection of the redundant line
818
is enabled.
At this time, when information of the fuses
810
in the address selection circuits
814
a
and
814
b
and information of address signals a
0
to a
i
input from the outside become equal, all signals ra
0
to ra
1
change to “H” level. As a result, the output
816
from the NAND circuit
815
changes to “L” level to disable the regular decoder. The signal of the redundant line
818
changes to “H” level, so that the redundant line is selected.
FIGS. 9A
to
9
D show the arrangement of the fuse interconnection. An interlevel insulating film
901
is formed on interconnection layers and the like formed on predetermined elements, and metal interconnections
902
made of Al or the like are formed on the interlevel insulating film
901
. The metal interconnections
902
serve as the fuse interconnections.
An interlevel insulating film
903
and a passivation film
904
are formed on the metal interconnections
902
. An opening portion
905
is formed at a predetermined position of the passivation film
904
to extend to an intermediate portion of the interlevel insulating film
903
. The opening portion
905
is formed to shorten the distance from the surface to the metal interconnections
902
.
Disconnection of the metal interconnections
902
will be described. As shown in the plan view of
FIG. 9B
, disconnection of the metal interconnections
902
is performed by irradiating a laser beam having an aperture size of about 2.5 &mgr;m
2
to predetermined laser irradiation regions
906
on the metal interconnections
902
in the opening portion
905
. This laser irradiation is performed for 20 ms to 100 ms in a pulse manner.
This laser irradiation disconnects (by fusion) the metal interconnections
902
into metal interconnections
902
a
and
902
b
, as shown in FIG.
9
C.
The irradiated portions of the metal interconnections
902
which are subjected to laser irradiation evaporate instantaneously. As a result, the metal interconnections
902
are fusion-disconnected by laser irradiation. Since this evaporation takes place explosively, it blows off part of the interlevel insulating film
901
and part of the interlevel insulating film
903
under and on the metal interconnections
902
to form holes
907
.
Although the metal interconnections
902
serving as the fuse interconnections are conventionally fusion-disconnected, as described above, they cannot often be disconnected electrically.
More specifically, although the metal interconnections
902
are fusion-disconnected by laser irradiation, the metal material that evaporates during laser irradiation is deposited on the side walls of the holes
907
again to form metal films
908
.
As shown in
FIGS. 9C and 9D
, since the metal films
908
are formed on the entire portions of the side walls of the respective holes
907
, the metal interconnections
902
a
and
902
b
that are fusion-disconnected are electrically connected to each other through the metal films
908
.
According to a conventional technique, an interconnection made of polysilicon is used as the fuse interconnection (for example, Japanese Patent Laid-Open No. 6-53323). Since polysilicon can be disconnected easily by laser irradiation and is not easily deposited again, the problem as described above does not arise easily.
However, to form a polysilicon interconnection, a high-temperature atmosphere is required. If an interconnection employing a metal is formed as the underlying layer, it is melted by the high-temperature atmosphere employed for formation of the polysilicon interconnection on it. For this reason, a polysilicon interconnection cannot accordingly be formed. When polysilicon is employed as the material of the fuse interconnection, the polysilicon fuse interconnection must be arranged as the lowest layer.
More specifically, when polysilicon is used as the material of the fuse interconnection and large numbers of interconnection layers and interlevel insulating films are formed on the polysilicon fuse interconnection, a deep opening portion must be formed to disconnect the fuse interconnection. When polysilicon is to be employed as the material of the fuse interconnection, the entire process is complicated and controllability for the remaining portion of the interlevel insulating film on the fuse interconnection is degraded, so that the fuse disconnection hit rate is extremely lowered.
SUMMARY OF THE INVENTION
The present invention has been made to solve the above problem, and has as its object to facilitate control for the remaining portion of an interlevel insulating film on a fuse interconnection without complicating the process and to improve a fuse disconnection hit rate.
In order to achieve the above object, according to the present invention, there is provided a semiconductor device comprising a fuse constituted by a lower interconnection formed on a semiconductor substrate, an upper metal interconnection formed on the lower interconnection through an interlevel insulating film to have an overlap region that overlaps at least part of the lower interconnection, and a conductor portion formed in the overlap region to electrically connect the upper metal interconnection and the lower interconnection to each other.
RE
Everhart Caridad
NEC Corporation
Young & Thompson
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