Semiconductor device and method of manufacturing same

Active solid-state devices (e.g. – transistors – solid-state diode – Thin active physical layer which is – Heterojunction

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257 30, 257 38, 257 46, 257104, 257136, 257498, 257458, 257523, 437 40, 437 81, 437105, 437107, 437126, 437228, H01L 2906, H01L 21265

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054850177

ABSTRACT:
A semiconductor device has an n.sup.+ source region, a first n.sup.- channel region, a barrier layer, a second n.sup.- channel region, a pair of n.sup.+ drain regions, an insulating film, and a pair of metal electrodes over the respective n.sup.+ drain regions, all successively disposed on an upper surface of an n.sup.+ crystal substrate. The drain regions and the metal electrodes jointly provide a storage electric capacitance. A source electrode is disposed on the lower surface of the n.sup.+ crystal substrate. Bit information can be written and read at a high speed by tunneling through the barrier layer. According to a method of manufacturing the above semiconductor device, the n.sup.+ source region, the first n.sup.- channel region, the barrier layer, the second n.sup.- channel region, the n.sup.+ drain regions, the insulating film, and the metal electrodes are successively deposited on the n.sup.+ crystal substrate in a growing apparatus. The metal electrodes and the source electrode are formed by depositing a metal and a low-resistance semiconductor selectively or both in one location within the growing apparatus.

REFERENCES:
patent: 4841350 (1989-06-01), Nishizawa
patent: 5216262 (1993-06-01), Tsu
Nishizawa et al., "High Speed and High Density Static Induction Transistor Memory" (Oct. 1978), IEEE Journal of Solid-State Circuits, vol. SC-13, No. 5, pp. 622-634.

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