Semiconductor device and method of making same

Details Semiconductor device and method of making same Semiconductor device and method of making same

2001-05-09

2003-11-25

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making device or circuit responsive to nonelectrical signal

Responsive to electromagnetic radiation

C438S022000, C438S042000, C438S077000, C438S902000, C438S962000, C257S012000, C257S014000, C257S018000, C257S019000, C257S021000, C257S085000, C257S094000, C257S190000

Reexamination Certificate

active

06653166

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention pertains to the field of semiconductor devices. More particularly, the invention pertains to semiconductor light sources, photodetectors and resonant tunneling devices, which have a large lattice mismatch between a substrate and an active region.
2. Description of Related Art
The problem of lattice matching of constituent materials in semiconductor heterostructures is critically important. The first double heterostructure laser, realized using lattice-mismatched GaAs-GaAsP materials, did not perform well enough to be used in practical applications. Progress in this area began only after lattice-matched heterostructures were developed, lasers with low room temperature threshold current density were obtained, and continuous wave operation at room temperature was achieved.
Only relatively small lattice mismatch can be tolerated in high-performance devices, for example, in a GaAs-AlGaAs heterostructure. In the case of a small lattice mismatch, the growth of the layer occurs pseudomorphically, or irregularly, and the layer accumulates significant strain energy. For example, W. T. Tsang, in Applied Physics Letters 38(9), May 1, 1981, pp. 661-663, described a GaAs/AlGaAs heterostructure laser having an InGaAs active layer. The indium was incorporated into the active layer in order to increase the output wavelength up to 0.94 &mgr;m. After a certain thickness, or composition, however, the strain energy becomes very high, and dislocations start to form, which ruins device performance. The critical thickness for dislocation formation rapidly decreases with increases in the lattice mismatch. For InGaAs-GaAs layers, this results in a fast degradation of luminescence properties at InGaAs layer thickness corresponding to the practically important wavelength range of 1.3-1.6 &mgr;m.
Dislocations take a negligibly small surface area of the plastically relaxed layer. The regions between the dislocations may remain structurally and optically perfect and their sizes may approach micrometer-scale sizes even with high lattice mismatch and thick plastically-relaxed layers.
The exact thickness for dislocation formation, the density of dislocations formed after plastical relaxation, and the degree of deterioration of optical properties may depend on particular surface morphology and deposition conditions. Under certain growth sequences, bright luminescence in the range of up to 1.35 &mgr;m may be realized at room temperature using highly strained InGaAs quantum wells and up to 1.7 &mgr;m using thicker graded-composition InGaA layers on GaAs substrates. Injection lasing has been demonstrated at 1.17 &mgr;m using an InGaAs quantum well grown on top of the GaAs-inserted strained ultrathin InGaAs buffer layer. Prior attempts to move the lasing wavelength further using InGaAs quantum wells have failed. So, in order to utilize longer wavelengths using GaAs substrates, it became necessary to use either different materials systems, such as InGaAsN-GaAs or GaAsSb-GaAs, or to apply different growth approaches, such as using an effect of elastic strain relaxation in Stranski-Krastanow growth mode. This process, accompanied by overgrowth of the islands formed may result in formation of strained coherent nanodomains, also called quantum dots, emitting up and beyond 1.3 &mgr;m.
However, these approaches do not yield a device with practically-acceptable parameters, cost-effective and reliable technology, and also result in formation of dislocations and other defects (e.g. dislocation loops, defect dipoles, dislocated clusters).
Numerous patents have tried to overcome the problem of lattice mismatch in fabricating semiconductor heterostructure devices. U.S. Pat. Nos. 5,960,018, 5,075,744, and 5,719,894, for example, used strain-compensation regions inside or near the active region of the device. Other patents, such as U.S. Pat. Nos. 5,019,874, 5,208,182, 5,927,995 and 5,091,767, each used dislocation filtering techniques to prevent dislocation propagation in the active layer or reducing their density. U.S. Pat. Nos. 5,156,995, 5,859,864, and 4,806,996 used complicated growth methods on profiled substrates. All these approaches, however, led only to a limited success, or were not cost-effective.
Therefore, there is a need in the art for a method which eliminates local regions of the relaxed semiconductor structure in the vicinity of dislocations in situ, without any of the additional processing steps which are required in the prior art.
SUMMARY OF THE INVENTION
A method of in-situ fabrication of dislocation-free structures from plastically relaxed layers grown on a semiconductor surface suitable for epitaxial growth is disclosed. This method solves the problem of lattice-mismatched growth.
The method produces coherent dislocation-free regions from initially dislocated and/or defect-rich layers lattice mismatched with respect to the underlying substrate, which does not contain any processing steps before or after formation of the defect-free-regions. The process preferably uses in situ formation of a cap layer on top of a dislocated layer. The cap layer preferably has a lattice parameter close to that in the underlying substrate, and different from that in the lattice mismatched epilayer in the no-strain state. Under these conditions, the cap layer undergoes elastic repulsion from the regions in the vicinity of the dislocations, where the lattice parameter is the most different from that in the substrate. The cap layer is absent in these regions. When the cap layer has a lower thermal evaporation rate than the underlying dislocation layer, the regions of this dislocation layer in the vicinity of dislocations are selectively evaporated at sufficiently high temperatures, and only the coherent defect-free regions of the initially-dislocated epilayer remain on the surface. In one embodiment of the invention, the size of the defect-free regions are preferably tuned in the range of 30-1000 &mgr;m, depending on the annealing conditions, thickness of the cap layer, and the lattice mismatch. A device created by this method is also disclosed.


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