Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead
Reexamination Certificate
2001-10-23
2004-11-16
Fahmy, Wael (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
C257S736000, C257S737000, C257S774000, C438S059000, C438S064000
Reexamination Certificate
active
06818986
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device in which a defective portion of a semiconductor chip provided with an electronic circuit integrated in high density (hereinafter referred to as “IC chip”) can be easily analyzed by a photo-emission analyzing method, and particularly to a surface mount type semiconductor device in which a plurality of electrode bumps are provided in the form of a ball grid array (BGA) and which is packaged.
First, referring to the figures, the structure of a general BGA package type semiconductor device will be conceptually described.
FIG. 2
is a sectional side view of a thermal enhanced BGA package type semiconductor device, and
FIG. 3
is a sectional side view of a plastic molded BGA package type semiconductor device.
A thermal enhanced BGA package (hereinafter referred to as “E-BGA”) type semiconductor device (hereinafter referred to simply as “IC”)
20
shown in
FIG. 2
comprises an IC chip
21
fixed to the back side of a metallic substrate
22
in an opening portion
24
formed at a central portion of a package substrate
23
laminated on the metallic substrate
22
, with the side of power source, ground wiring and the like as well as a plurality of electrodes (not shown) of the IC chip
21
directed downward (hereinafter referred to “face-down”), wherein the electrodes are connected by wires
27
to electrode lands (not shown) provided on the package substrate
23
, and the IC chip
21
is sealed with a sealing material
25
. The package substrate
23
may be a monolayer substrate, but generally is of a multi-layer laminate substrate structure, and a plurality of electrode bumps
26
made of solder in ball shape are provided in a predetermined grid-like array on the back side of the lowest layer of the multi-layer substrate.
A plastic molded BGA package (hereinafter referred to as “P-BGA”) type IC
30
shown in
FIG. 3
comprises an IC chip
31
fixed on a package substrate
32
provided with wirings such as electrode lands (not shown), with the side of power source, ground wirings and the like as well as a plurality of electrodes (not shown) of the IC chip
31
directed upward (hereinafter referred to as “face-up”), wherein the electrodes are connected by wires
33
to electrode lands (not shown) of the package substrate
32
, and the IC chip
31
in such condition and the surface inclusive of the electrode lands of the package substrate
32
are sealed with a sealing resin
34
. The package substrate
32
has the same structure as that of the package substrate
23
, and a plurality of electrode bumps
35
are provided in a predetermined grid-like array on the back side of the lowest layer of the package substrate
32
.
The E-BGA package type IC
20
(hereinafter referred to simply as “IC 20”) and the P-BGA package type IC
30
(hereinafter referred to simply as “IC 30”) are finally subjected to quality test in a factory, and then sold to the users such as an assembly maker. The user surface-mounts the IC
20
or IC
30
onto the user's electronic circuit substrate by utilizing a substrate or taping.
As shown in
FIG. 2
, the IC
20
is surface mounted on the user's electronic circuit substrate in the condition where the metallic substrate
22
is disposed on the upper side and the IC chip
21
is directed downward (face-down) so as to enhance heat radiation properties. As shown in
FIG. 3
, the IC
30
is surface mounted on the user's electronic circuit substrate in the condition where the IC chip
31
is present on the upper side of the package substrate
32
(face-up).
After the IC
20
or IC
30
is mounted, or during the mounting, defective mounting or potential defects present in the IC
20
or IC
30
itself come to appear upon mounting, and the defective IC
20
or IC
30
is returned to the semiconductor maker side. On the semiconductor maker side, the reason of failure or defects in the IC
20
or IC
30
thus returned is analyzed. The analysis is usually carried out by a photo-emission analyzing method.
The photo-emission analyzing method is a method of determining the position of failure on the IC chip in the case where the IC failure mode is a DC characteristic failure such as latch-up and junction collapse. In the case of a MOS type IC, little current flows through a PN junction of a normal transistor, but, in the case of the failure mode, a large quantity of junction current flows, and an excess of the current generates far infrared rays, which are detected by a special detector to thereby determine the position of failure. Although far infrared rays are radiated also in the case of heat generation due to short-circuit of metallic components at wiring portions, the wavelength band in such failure is different from that in the case of the above-mentioned failure mode, so that observation of the far infrared rays is carried out by switching over the wavelength sensitivity.
As has been described above, in the photo-emission analyzing method, it is necessary to detect the far infrared rays coming from a PN junction portion of the transistor. Where the number of aluminum wiring layers provided on the upper side of the PN junction portion is larger, the wirings intersect complicatedly with each other in a network form, so that the far infrared rays radiated from the lowest layer are blocked by the wirings when observed from the face side of the IC chip. Therefore, where the IC chip is formed in a multi-layer wiring structure, observation from the face side of the IC chip is impossible.
However, the far infrared rays can pass through bulk silicon, so that observation of far infrared rays is carried out from the back side of the IC chip opposite to the wiring layer side.
At the time of analyzing a defective IC, power source is applied so as to obtain a normal IC chip operation mode, and analysis is conducted by holding the IC chip in a timing suitable for easy determination.
Therefore, in the case of the IC
20
, cutting the metallic substrate
22
has some influence on heat radiation properties but has no influence on the operation of the IC chip
21
, so that radiation of far infrared rays can be observed by mechanically cutting the metallic substrate
22
at the portion where the IC chip
21
is present.
In the case of a normal quad flat package (QFP) type IC, the IC chip is constituted by face-up bonding, and, therefore, the mold is cut from the back side, and finally a lead frame is cut to expose the back side of the IC chip (effective signal wires are ordinarily absent in the lead frame).
However, in the case of the IC
30
, although it is possible to cut the sealing resin
34
on the upper side of the IC chip
31
and expose the IC chip
31
, a power source wiring portion must be removed with a special chemical because a power source layer is provided on the surface of the IC chip
31
. The removal may increase the impedance of the power source wiring portion, and may remove necessary portions, resulting in some case in that the IC chip
31
does not operate actually. In addition, as has been describe above, the observation of the far infrared rays from the side of the sealing resin
34
is hampered by the layers of aluminum wirings on the upper side of PN junctions of the IC chip
31
. Namely, the aluminum wirings appear as complicated intersections in a network form as viewed from the side of the sealing resin
34
, so that far infrared rays are shut off, and analysis by photo-emission is impossible.
On the other hand, at the time of observing the far infrared rays from the back side (lower side) of the sealing resin
34
, the whole surface of the IC chip
31
is covered by the package substrate
32
, so that a central portion of the package substrate
32
where the IC chip is present must be cut away. The package substrate
32
naturally contains innumerable wiring patterns, so that it is impossible to easily remove the central portion of the package substrate
32
by cutting. It may be contemplated to design wiring so that wiring patterns are absent at a portion on th
Ikenaga Yuichiro
Otsuka Yasushi
Fahmy Wael
Kananen Ronald P.
Rader & Fishman & Grauer, PLLC
Rao Shrinivas H.
Sony Corporation
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