Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – With pn junction isolation
Reexamination Certificate
2001-09-21
2004-03-09
Zarabian, Amir (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
With pn junction isolation
C257S547000, C257S487000
Reexamination Certificate
active
06703684
ABSTRACT:
The present invention relates to a semiconductor device and to a method of forming a semiconductor device.
The present invention is particularly concerned with high voltage/power semiconductor devices which can be used as discrete devices, in hybrid circuits and in power integrated circuits and is particularly concerned with field-effect transistors, such as power MOSFETs, insulated gate bipolar transistors (IGBTs) and other types of power devices such as diodes, transistors and thyristors.
For devices designed for use in integrated circuits, it is preferred that the main terminals (variously called the anode/cathode, drain/source and emitter/collector) and the control terminals (termed the gate or base) are placed at the surface of the device in order to be easily accessible. The main current flow is between the main terminals and is therefore principally lateral. Such devices are therefore typically referred to as lateral devices. Such devices are often integrated with low-voltage devices or circuits built in CMOS-type or other standard planar technologies to form power integrated circuits. Several high voltage/power devices may be integrated in the same chip. Isolation is provided between the high-power and the low-power devices as well as between adjacent power devices. Two principal isolation technologies have emerged, namely junction-isolation (JI) technology and silicon-on-insulator (SOI) technology.
In JI technology, a reverse-biased junction is used to isolate adjacent devices. However, this is in many cases not satisfactory for power integrated circuits since minority carrier conduction through the semiconductor substrate (on which the active part of the device is formed) can take place and interference between adjacent devices is therefore difficult to prevent. In addition, JI bipolar devices (such as the lateral IGBT) also suffer from parasitic mobile carrier plasma stored in the semiconductor substrate in the on-state which has to be removed during turn-off. This decreases dramatically the switching speed of the devices.
In SOI technology, a buried insulating layer is used to isolate vertically the top semiconductor layer from the bottom semiconductor layer and, accordingly, current conduction is principally restricted to the top semiconductor layer and there is practically no current in the bottom semiconductor layer in any mode of operation. Horizontal or lateral isolation in SOI is typically provided via trenches which are filled with oxide or by use of the known LOCOS (“local oxidation of silicon”) isolation. SOI technology offers better isolation than JI technology because the buried insulating layer prevents current conduction and plasma formation in the substrate.
High voltage semiconductor devices have incorporated within the body of the device a high voltage junction that is responsible for blocking the voltage. This junction includes a relatively lowly doped semiconductor layer which withstands the largest portion of the voltage across the main terminals when the device is in the off-state and operating in the voltage blocking mode. This layer is commonly referred to as the drift region or layer and is partially or fully depleted of minority carriers during this operating mode. Ideally, the potential is equally distributed along the drift region between the two ends of the drift region. However, as shown by the 1-D Poisson equation, for a given doping of the drift region, the distribution of the electric field has a triangular shape or, when fully depleted, a trapezoidal shape. Since the area underneath the electric field can be approximated as the breakdown voltage when the peak of the electric field reaches the critical electric field in the semiconductor, it is obvious that for a 1-D junction, the lower the doping of the drift layer, the higher the breakdown voltage. However, for majority carrier devices such as MOSFET types, known as LDMOSFETs, the on-state resistance of the drift layer is inversely proportional to the doping of the drift layer. Since a low on-resistance is desired for a high voltage switch, it follows that a low doping concentration affects the on-state performance of the device. In addition for lateral devices, the critical electric field at the surface is smaller than in the bulk, adding further difficulties in designing high voltage lateral devices.
The introduction of the RESURF (Reduced Surface Field Effect) technique for JI devices allows an increase in the breakdown voltage of lateral devices through the use of an additional vertical junction formed between the drift region and the semiconductor substrate.
FIG. 1
a
shows schematically a conventional JI diode using the RESURF effect. This diode is provided as part of a conventional lateral power device such as a lateral transistor, LDMOSFET or LIGBT.
FIG. 1
a
also shows the distribution of the potential lines and the edge of the depletion region during the voltage blocking mode. It can be noted that the drift layer
1
is fully depleted but the semiconductor substrate
2
is not fully depleted. The potential lines bend as they drop in the substrate, from the vertical direction towards the horizontal direction, such that below the high voltage terminal
3
, the potential lines are practically parallel to the bottom surface
4
of the substrate
2
. This is because the thickness of the semiconductor substrate
2
is relatively large (typically 300 &mgr;m) compared to the vertical extension of the depletion region from the top surface
5
into the substrate
2
(typically 60 &mgr;m for a 600V device). Hence, the semiconductor substrate
2
is not fully depleted when the breakdown of the device occurs. It is known that a lateral JI diode can achieve breakdown voltages equivalent to those of vertical diodes, in spite of the reduced surface critical electric field. Nevertheless, as shown in
FIG. 1
a,
even an optimised electric field distribution using the RESURF concept is far from being ideal (i.e. rectangular in shape). In addition as already mentioned, the JI devices suffer from high leakage currents and very poor isolation, which makes integration within a power integrated circuit very difficult.
FIG. 1
b
shows a conventional SOI diode which is typically found as part of a SOI lateral high voltage power device. The structure can be made using the known wafer bonding, Unibond or SIMOX SOI technologies. Other technologies such as Silicon-on-Diamond (SOD) are also known.
FIG. 1
b
also shows the equi-potential line distribution during the voltage blocking mode. It can be seen that the potential lines crowd towards the edges of the drift layer
1
, resulting in a poor RESURF effect. Increasing the thickness of the buried oxide
6
helps to redistribute the potential lines more evenly at the top surface
5
. However, in general, the breakdown voltage is still below that of a JI device or JI diode as shown in
FIG. 1
a.
Again, the potential lines in the drift layer
1
and the buried silicon oxide insulating layer
6
below the high voltage terminal are practically aligned to the horizontal surface. This is due to the fact that the semiconductor substrate
2
is not entirely depleted. The result is that all the potential lines have to crowd into the drift layer
1
and insulating layer
6
in the case of SOI and moreover have to align parallel to the insulating layer
6
/semiconductor substrate
2
interface. This creates an uneven distribution of the potential lines at the top surface
5
which results in high electric field peaks and therefore lower breakdown voltages. In addition, for SOI devices, the conservation of the perpendicular component of the electric flux density D=∈E at the top of the semiconductor layer
1
/buried oxide
6
interface limits the maximum voltage that the buried oxide
6
can sustain before the critical electric field in the semiconductor layer
1
at the interface is reached. This vertical breakdown yields a very strong limitation on the maximum voltage rating achievable for a given buried oxide thickness.
Thus, in summary, in both J
Amaratunga Gehan A. J.
Udrea Florin
Cambridge Semiconductor Limited
Rose Kusha
Zarabian Amir
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