Semiconductor device and method of fabrication thereof

Details Semiconductor device and method of fabrication thereof Semiconductor device and method of fabrication thereof

2000-10-05

2002-12-10

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Encapsulating

C438S112000, C438S126000

Reexamination Certificate

active

06492203

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is related to a semiconductor device and a method of fabrication thereof.
2. Description of the Related Art
There is a growing need for a smaller semiconductor device package with multiple terminal pins due to increases of an integration rate and an operation frequency in the recent semiconductor device. However, a package size of a conventional peripheral terminal type utilizing a leadframe has to be made larger if a number of the terminals should be increased further. One of countermeasures is to decrease a terminal pitch in the package. However, it is difficult to make the terminal pitch narrower than 0.4 mm.
To accommodate such increasing number of the terminals, an area array type package with its terminals disposing over a surface plane is introduced. The area array type package requires to have a wiring substrate for providing wiring from chip terminals to external terminal electrodes. The chip may be mounted either at the upper surface or the lower surface of the wiring substrate when the external terminal electrodes are disposed at the lower surface of the wiring substrate. When the chip is mounted on the upper surface of the wiring substrate, interlayer connections between the upper surface and the lower surface of the wiring substrate have to be provided. When the chip is mounted on the lower surface of the wiring substrate, the interlayer connections will not be required. However, a hollow space has to be provided to absorb total thickness of the chip and its sealing material when the chip is mounted on the lower surface of the wiring substrate.
The hollow space is called a cavity, and a structure with the cavity at the lower surface of the wiring substrate is called a cavity down structure. Typically, the structure can be made by hollowing out a substrate, or by making a hole through the substrate and adhering a base plate thereto. Wiring for a multiple layer structure is required when heights of chip bonding portions and external electrodes are changed because the wiring is also disposed on the same surface in this structure. According to the methods described above, a wiring structure, which satisfies required conditions for a three dimensional spatial relationships among the chip mount portion, the chip bonding portion and the external electrode portion.
One of the area array type semiconductor package is Ball Grid Array (BGA) in which solder balls are used as connection terminals. Cost of the BGA is higher than that of a semiconductor device fabricated with a conventional leadframe, and reduction of the cost is anticipated. The higher cost is due to a fact that a structure and fabricating process of the semiconductor chip package substrate are more complex than that of a substrate with the leadframe. Accordingly, it is anticipated the development of simpler structure and fabricating process of the semiconductor chip package substrate.
The wiring substrate used for the area array type semiconductor package is typically called an interposer. The interposer may be roughly classified into a film type and a rigid type. A number of the wiring layers can be either one, or two, or three and more layers. Generally, the fabricating cost is lower for a fewer number of the wiring layers.
The lowest cost is expected with the single layer wiring structure. If the wiring is disposed at least in both surfaces of the interposer, the semiconductor chip mount portion and the external terminals may be divided at the upper and the lower surfaces. However, the semiconductor chip mount portion and the external terminals are disposed on the same surface of the interposer with the single layer wiring structure. In such a single layer wiring structure, it is required to have the cavity portion on the wiring surface with a depth at least comparable to a thickness of the chip so as to store the chip therein. A method of fabricating such a cavity portion has become an important subject.
In the interposer so called TAB (Tape Automated Bonding) or TCP (Tape Carrier Package) and their packaging technology, the center portion of the interposer is bored through to store the semiconductor chip. With the rigid plate, the center portion of the interposer is similarly bored through to hollow the semiconductor chip store portion out and adhere a metal plate as the base plate thereto, or the cavity portion is fabricated at the center portion of the interposer. The wiring is disposed only in a flat plane portion, not inside the cavity portion.
In conventional semiconductor devices employing lead frames, transfer molding has been in wide use for their fabrication. However, in the fabrication of semiconductor devices in recent years where semiconductor chips are mounted on substrates, the transfer molding, which requires expensive and long-time-to-delivery molds, has become adaptable with difficulty though still used in some cases, because it is difficult for the substrates used and package structure to be standardized.
Accordingly, liquid resin encapsulation (sealing) is highlighted which requires no mold and is suited especially when small quantity and many kinds of products are manufactured in a short time to delivery. Dispensing, printing and vacuum pressure differential printing are known as chief methods for such encapsulation making use of a liquid resin encapsulant (sealant).
FIG. 24C
perspectively illustrates an encapsulation target where a semiconductor chip
1
is mounted on a substrate
7
and this chip
1
and a conductor wiring
2
are connected through wires
3
by wire bonding. In conventional dispensing, as shown in
FIG. 24A
, a solder resist
25
is provided on the surface of the conductor wiring
2
of this chip-mounting substrate. On that surface an encapsulation dam
26
is provided as shown in
FIG. 24B
, and a liquid resin encapsulant
4
is poured therein to encapsulate the chip
1
as shown in FIG.
24
D. In this method, however, especially in the case of fine-pitch wire bonding, the resin encapsulant
4
may come around with difficulty beneath the wires
3
at the time of encapsulation to tend to cause encapsulation defects
20
such as air bubbles and faulty filling, also resulting in a low productivity.
Printing is known as a liquid resin encapsulation method that can achieve a productivity comparable to that of transfer molding. The printing is a method in which as shown in
FIG. 25A
an encapsulant
4
is printed via a printing mask
28
and thereafter as shown in
FIG. 25B
the printing mask
28
is removed, whereby a chip
1
is encapsulated. This method promises a high productivity, but, in the case of fine-pitch wire bonding, tends to cause encapsulation defects
20
such as faulty filling and air bubbles beneath bonded wires
3
or at the part with complicated or delicate internal structure.
As a method for solving this problem to achieve improvement greatly, there is vacuum pressure differential printing, which has been invented so that printed portions with complicated internal structure can be filled with a printing resin without leaving any air bubbles.
In this method, the whole printing portions, i.e., part or the whole of a printing device, a printing mask
28
, a liquid resin encapsulant
4
, and a printing-target wiring substrate
1
with a semiconductor chip mounted thereon, and so forth, are placed in a vacuum container, where first-time printing is carried out firstly in the state the vacuum container is kept at a high vacuum (FIG.
26
A). When left in this state, any delicate areas of printed portions can be filled with the resin with difficulty, so that an empty space
21
may remain.
Accordingly, the vacuum container is then brought to medium-vacuum condition, whereupon the high-vacuum empty space
21
not filled with the resin at the first-time printing is crushed up to the medium-vacuum condition to become almost free of the empty space
21
and simultaneously a depression
22
a
appears at the resin surface to an extent corresponding to the resin with which the open space h

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