Active solid-state devices (e.g. – transistors – solid-state diode – Bipolar transistor structure – With specified electrode means
Reexamination Certificate
1999-08-06
2001-12-18
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Bipolar transistor structure
With specified electrode means
C257S588000, C257S592000
Reexamination Certificate
active
06331727
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a method of fabricating the same and, more particularly, to the structure of a bipolar transistor and a method of fabricating the same.
Recently, bipolar transistors are used in a wide variety of applications such as computers, optical communications, and various analog circuits. The following references have proposed bipolar transistors using the epitaxial techniques. The cutoff frequency of these bipolar transistors fabricated on an experimental basis almost reaches 60 GHz.
(1) IEEE Trans on Electron Device, Vol. ED-38, Feb. 1991, p. 378
(2) IEDM′90, p. 13
(3) Japanese Patent Laid-Open No. 05-175222
A method of fabricating an npn bipolar transistor according to one prior art will be described below with reference to the accompanying drawings (
FIGS. 1
to
14
).
First, as shown in
FIG. 1
, an n
+
-type diffusion layer
2
is formed on a p-type silicon substrate
1
using, e.g., ion implantation. Epitaxial growth is then used to form an n
+
-type silicon layer
3
on the upper surface of the n
+
-type diffusion layer
2
formed on the p-type silicon substrate
1
. Next, by a predetermined etching step, a shallow trench about a few hundred nm deep is formed. A normal film formation step and planarization process are used to bury an insulating film
4
, such as a silicon oxide film, in this shallow trench. Consequently, an element isolation region is completed.
Next, as shown in
FIG. 2
, epitaxial growth is used to form a p-type silicon film
5
as a base electrode on the entire surface. In addition, a silicon oxide film
6
is formed on the entire surface using CVD. Spin coating is then used to form a resist (not shown) on the upper surface of the silicon oxide film
6
. This resist is patterned into a predetermined shape by using photolithography. Furthermore, this resist is used as a mask to pattern the silicon oxide film
6
into a predetermined shape by RIE. After that, the resist (not shown) is removed by ashing.
As illustrated in
FIG. 3
, CVD is used to form a polysilicon film on the entire surface. Ion implantation is then performed to dope a p-type impurity, e.g., B (boron) into the entire surface. This B (boron) is thermally diffused to change the polysilicon film into a p-type impurity doped polysilicon film
7
(to be referred to as a “p-type polysilicon film
7
” hereinafter).
As shown in
FIG. 4
, spin coating is used to form a resist
8
on the upper surface of the p-type polysilicon film
7
. This resist
8
is patterned into a predetermined shape by using photolithography.
As depicted in
FIG. 5
, the resist mask
8
is used as a mask to etch the p-type polysilicon film
7
and the p-type silicon film
5
by anisotropic etching, e.g., RIE. During this etching, the insulating film
4
is used as an etching stopper. After that, the resist
8
is removed by ashing.
As shown in
FIG. 6
, a resist
9
is formed on the entire surface by using spin coating. This resist
9
is formed into a predetermined shape by using photolithography. Furthermore, ion implantation is performed using the resist
9
as a mask to dope an n-type impurity, e.g., P (phosphorus) into the entire surface. Consequently, a portion of the p-type polysilicon film
7
on which the resist
9
is not formed and the p-type silicon film
5
below this portion form an n-type polysilicon film
10
and an n-type silicon film
11
, respectively.
As illustrated in
FIG. 7
, the resist
9
is removed by ashing. CVD is used to form a silicon oxide film
12
on the entire surface. CVD is used again to form a silicon nitride film
13
on the entire surface.
As shown in
FIG. 8
, a resist (not shown) patterned into a predetermined shape on the upper surface of the silicon nitride film
13
is used as a mask to etch the silicon nitride film
13
and the silicon oxide film
12
by RIE. This exposes a portion of the upper surface of the p-type polysilicon film
13
. In addition, the silicon nitride film
13
is used as a mask to etch the p-type polysilicon film
7
by RIE. Consequently, a contact hole
14
is formed to partially expose the upper surface of the silicon oxide film
6
.
Next, a step shown in
FIG. 9
is performed. That is, CVD is used to form a silicon nitride film
15
on the entire surface. This silicon nitride film
15
is etched by using anisotropic etching, e.g., RIE. Consequently, the silicon nitride film
15
remains only on the side surfaces of the contact hole
14
, and the upper surface of the silicon oxide film
6
is partially exposed. This exposed portion of the silicon oxide film
6
is removed by wet etching to expose the p-type silicon film
5
.
As shown in
FIG. 10
, CVD is used to form a polysilicon film on the entire surface. Ion implantation is then performed to dope an n-type impurity, e.g., As (arsenic) into the entire surface by using the silicon nitride films
13
and
15
as masks. This As (arsenic) is thermally diffused to change the polysilicon film into an n-type polysilicon film
16
.
As shown in
FIG. 11
, a resist (not shown) patterned into a predetermined shape on the upper surface of the n-type polysilicon film
16
is used as a mask to etch the n-type polysilicon film
16
by anisotropic etching, e.g., RIE. This etching is so performed that the n-type polysilicon film
16
is buried in the contact hole
14
. Also, in this etching step, the silicon nitride film
13
is used as an etching stopper. After the etching, the resist (not shown) is removed by ashing.
Next, a step shown in
FIG. 12
is performed. That is, a resist (not shown) is patterned into a predetermined shape on the entire surface by exposure and development. This resist and the n-type polysilicon film
16
are used as masks to etch the silicon nitride film
13
and the silicon oxide film
12
into a predetermined shape by anisotropic etching, e.g., RIE. During this etching, the p-type polysilicon film
7
and the n-type polysilicon film
10
are used as etching stoppers. After the etching, the resist (not shown) is removed by ashing.
As depicted in
FIG. 13
, a titanium film is formed on the entire surface by sputtering. Annealing is then performed to react this titanium film with the p-type polysilicon film
7
, the n-type polysilicon film
16
, and the n-type polysilicon film
10
. Consequently, a titanium silicide film
17
is formed.
Finally, as shown in
FIG. 14
, CVD is used to form a TEOS film
19
on the entire surface. After that, although not shown, a contact is formed in this TEOS film
9
where necessary.
An npn bipolar transistor is formed as described above. The structure of this npn bipolar transistor will be described below with reference to FIG.
14
. Referring to
FIG. 14
, a base extraction electrode is constructed of the p-type silicon film
5
and the p-type polysilicon film
7
. An emitter extraction electrode is made of the n-type polysilicon film
16
. A collector region is composed of the n-type silicon layer
3
and the n
+
-type diffusion layer
2
. A collector extraction electrode is made up of the n-type silicon film
11
and the n-type polysilicon film
10
.
The width of the n-type silicon layer
3
below the p-type silicon film
5
is about 900 nm. The width of the n-type silicon layer
3
below the n-type polysilicon film
10
as a collector is about 1,400 nm. The width of the insulating film
4
sandwiched between these n-type silicon layers
3
is about 2,400 nm. Furthermore, a distance of about 1,000 nm is necessary between this npn bipolar transistor and each of element isolation regions so formed as to sandwich the transistor. Accordingly, the width of the whole element is about 6 to 7 &mgr;m.
In this prior art, as already shown in the step of
FIG. 8
, to form the n-type polysilicon film
16
as the emitter extraction electrode, the contact hole
14
must be formed by the etching step. However, if misalignment occurs in this etching step, the formation position of the contact hole
14
deviates.
Assume, for example, that the formation position of the
Nakajima Hiroomi
Sakamoto Toshihiro
Kabushiki Kaisha Toshiba
Meier Stephen D.
Pillsbury & Winthrop LLP
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