Semiconductor device and method of fabricating the same

Active solid-state devices (e.g. – transistors – solid-state diode – With means to control surface effects – Insulating coating

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Details

257635, 257637, 257774, 257750, 257758, H01L 2358, H01L 2348, H01L 2352

Patent

active

060694009

ABSTRACT:
A semiconductor device having a multi-level interconnection structure is disclosed which includes a metal interconnect wire (2) formed on a surface of an interlayer dielectric film (7) serving as a base; a high-stress TEOS oxide film (5), an SOG film (3), and a low-stress TEOS oxide film (6) which are deposited as interlayer dielectric films; and a contact hole (4), thereby decreasing stresses applied from the interlayer dielectric films to the metal interconnect wire to prevent metal hillocks in the contact hole.

REFERENCES:
patent: 4734754 (1988-03-01), Nikawa
patent: 4984060 (1991-01-01), Ohmi et al.
patent: 5567660 (1996-10-01), Chen et al.

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