Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2002-07-19
2004-04-20
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S425000, C438S435000, C438S437000, C438S444000, C438S452000, C257S506000, C257S510000, C257S647000
Reexamination Certificate
active
06723615
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly, it relates to a semiconductor device having a trench for element isolation and a method of fabricating the same.
2. Description of the Prior Art
A semiconductor device employing trench isolation for isolating semiconductor elements formed on a semiconductor substrate from each other is known in general.
FIG. 21
is a sectional view of such a conventional semiconductor device. Referring to
FIG. 21
, a thermal oxide film
102
is formed on a surface of a p-type silicon substrate
101
expressed by the (001) plane. A plurality of n-type impurity regions
121
are formed on the surface of the silicon substrate
101
. The n-type impurity regions
121
are isolated from each other by a trench
187
formed on the surface of the silicon substrate
101
and a silicon oxide film
109
filling up the trench
187
. Such isolation is referred to as shallow trench isolation (STI). The n-type impurity regions
121
are employed as source/drain regions of a field-effect transistor, for example.
A problem in the conventional semiconductor device is now described.
FIG. 22
is a sectional view showing the problem caused in the conventional semiconductor device. Referring to
FIG. 22
, an interlayer isolation film
120
is generally formed on the silicon substrate
101
. A contact hole
120
h
is formed to be connected with one of the n-type impurity region
121
. The contact hole
120
h
, formed not to reach the trench
187
in general, may reach the trench
187
due to some cause, as shown in FIG.
22
. An n-type impurity is injected into the silicon substrate
101
through the contact hole
120
h
. This injection is referred to as SAC (self-aligned contact) injection. A plug layer
123
is formed to fill up the contact hole
120
h.
However, the side wall of the trench
187
is so steeply inclined with respect to the silicon substrate
101
that it is difficult to form a homogeneous diffusion layer of the n-type impurity on the side wall of the trench
187
by SAC injection. Therefore, the p-type silicon substrate
101
or a p-type well region formed on the silicon substrate
101
is exposed on the portion of the silicon substrate
101
facing the trench
187
. The plug layer
123
electrically connects the n-type impurity region
121
and the p-type silicon substrate
101
with each other. While no current flows from the n-type impurity region
121
to the p-type silicon substrate
101
in general, a current flows from the n-type impurity region
121
to the p-type silicon substrate
101
through the plug layer
123
in the structure shown in
FIG. 22
, leading to generation of a leakage current. Thus, the semiconductor device is disadvantageously reduced in reliability.
SUMMARY OF THE INVENTION
Accordingly, the present invention has been proposed in order to solve the aforementioned problem, and an object thereof is to provide a semiconductor device having high reliability.
The semiconductor device according to the present invention comprises a semiconductor substrate having a main surface and including a trench formed on the main surface. The trench is defined by surfaces including a bottom surface, a side surface, continuous to the bottom surface, having first inclination with respect to the main surface and an intermediate surface, formed between the main surface and the bottom surface, having second inclination smaller than the first inclination with respect to the main surface. The semiconductor device further comprises an impurity region including a bottom surface having a depth from the main surface larger than the depth from the main surface to the intermediate surface with a surface defined by the intermediate surface.
In the semiconductor device having the aforementioned structure, the trench is defined by the surfaces including the intermediate surface having relatively small inclination. The impurity region includes the bottom surface having the depth larger than the depth from the main surface to the intermediate surface, and the surface of the impurity region is defined by the intermediate surface. When a plug layer comes into contact with the intermediate surface, therefore, the intermediate surface comes into contact with the impurity region, not in contact with a portion of the semiconductor substrate having an opposite conductivity type to the impurity region. Therefore, generation of a leakage current can be prevented for providing a highly reliable semiconductor device. Further, the impurity region is formed up to the portion of the intermediate surface, whereby formation of a depletion layer can be prevented on the portion of the intermediate surface. Consequently, this portion can be prevented from generation of a leakage current.
A method of fabricating a semiconductor device according to the present invention comprises steps of:
(1) forming a first silicon oxide film on a main surface of a semiconductor substrate;
(2) forming a polysilicon layer on the first silicon oxide film;
(3) forming a mask layer including a first opening having a first opening diameter on the polysilicon layer;
(4) selectively removing part of the polysilicon layer, part of the first silicon oxide film and part of the semiconductor substrate along the first opening through the mask layer serving as a mask thereby forming a second opening continuous to the first opening in the polysilicon layer, forming a third opening continuous to the second opening in the first silicon oxide film and forming a first cavity, defined by a side surface and a bottom surface, continuous to the third opening in the semiconductor substrate;
(5) oxidizing the portion of the polysilicon layer defining the second opening and the side and bottom surfaces of the first cavity for forming a second silicon oxide film having a side portion and a bottom portion while forming a second cavity receiving the second silicon oxide film in the semiconductor substrate;
(6) removing the bottom portion of the second silicon oxide film for exposing the bottom surface of the second cavity while leaving the side portion of the second silicon oxide film thereby forming a fourth opening, defined by the side portion, having an opening diameter smaller than the first opening diameter;
(7) selectively removing part of the semiconductor substrate along the fourth opening through the left side portion serving as a mask thereby forming a trench; and
(8) oxidizing the surface of the trench.
In the method of fabricating a semiconductor device comprising the aforementioned steps, the trench is formed by forming the second cavity and thereafter partially removing the semiconductor substrate along the fourth opening provided in the second cavity. Therefore, the trench has a portion having a large opening diameter formed by the second cavity and a portion having a small opening diameter formed by selectively partially removing the semiconductor substrate along the fourth opening. Also when a contact hole comes into contact with the portion having a large opening diameter formed by the second cavity, a homogeneous diffusion layer can be formed due to loose inclination of this portion. Consequently, generation of a leakage current can be prevented for providing a highly reliable semiconductor device.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5646063 (1997-07-01), Mehta et al.
patent: 5679599 (1997-10-01), Mehta
patent: 5721174 (1998-02-01), Peidous
patent: 6018180 (2000-01-01), Cheek et al.
patent: 6020621 (2000-02-01), Wu
patent: 6034409 (2000-03-01), Sakai et al.
patent: 6040231 (2000-03-01), Wu
patent: 6060399 (2000-05-01), Kim et al.
patent: 6165870 (2000-12-01), Shim et al.
patent: 6207532 (2001-03-01), Lin et al.
patent: 6274457 (2001-08-01), Sakai et al.
paten
Malsawma Lex H.
McDermott & Will & Emery
Smith Matthew
LandOfFree
Semiconductor device and method of fabricating the same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device and method of fabricating the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and method of fabricating the same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3266892