Semiconductor device and method of fabricating the same

Active solid-state devices (e.g. – transistors – solid-state diode – With means to control surface effects – Insulating coating

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257632, H01L 2358

Patent

active

055980279

ABSTRACT:
Disclosed herein is a semiconductor device, which can effectively prevent a lower insulating layer from formation of a recess resulting from etching during formation of a groove for connecting interconnection layers with each other. In this semiconductor device, a first etching prevention film is formed on a first interlayer insulating film, so that a second interlayer insulating film is formed on the first etching prevention film.

REFERENCES:
patent: 4443932 (1984-04-01), Mastroianni et al.
patent: 4832789 (1989-05-01), Cochran et al.
patent: 5235205 (1993-08-01), Lippitt, III
patent: 5321211 (1994-06-01), Haslam et al.
"A Four-Level-Metal Fully Planarized Interconnet Technology for Dense High Performance Logic and SRAM Applications", Ronald R. Uttecht et al., VMIC Conference, Jun. 11-12, 1991, pp. 20-26.
"Dual Damascene: A ULSI Wiring Technology", Carter W. Kaanta et al., VMIC Conference, Jun. 11-12, 1991, pp. 144-151.

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