Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Using epitaxial lateral overgrowth
Reexamination Certificate
1999-11-24
2003-02-18
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Using epitaxial lateral overgrowth
C438S481000
Reexamination Certificate
active
06521504
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a semiconductor device having layers formed by means of molecular beam epitaxy and a method of fabricating a semiconductor device by using an apparatus for carrying out molecular beam epitaxy.
2. Description of the Related Art
Japanese Unexamined Patent Publication No. 5-211158 has suggested a method of fabricating a semiconductor device by means of molecular beam epitaxy (hereinafter, referred to simply as “MBE”). Hereinbelow is explained the method with reference to
FIGS. 1A
to
1
D.
First, as illustrated in
FIG. 1A
, there is formed an N
−
epitaxial layer
2
over an N-type silicon substrate
1
. The N
−
epitaxial layer
2
has a thickness ranging from 0.8 to 1.3 &mgr;m, and a resistivity ranging from 0.5 to 1.0 &OHgr;-cm. Then, the N
−
epitaxial layer
2
is thermally oxidized to thereby form a silicon dioxide film
3
having a thickness of about 100 nm. Then, a part of the silicon dioxide film
3
is removed by photolithography and anisotropic etching to thereby form a base region. Then, silicon and boron are evaporated in an apparatus for carrying out molecular beam epitaxy (hereinafter, referred to simply as “MBE apparatus”) which provides about 10−
8
Torr vacuum to thereby form a P-type layer
4
on the N
−
epitaxial layer
2
at 650° C. of growth temperature. The P-type layer
4
has a thickness in the range of 30 to 50 nm, and a carrier concentration on the order of 10
18
cm
−3
. Hereinbelow, an layer formed by means of the MBE apparatus, including the P-type layer
4
, is referred to as “an MBE layer”.
Then, silicon and boron are evaporated again in the MBE apparatus to thereby form a P
−
MBE layer
5
over the P-type MBE layer
4
at 650° C. of growth temperature. The P
−
MBE layer
5
has a thickness in the range of 5 to 20 nm. The P
−
MBE layer
5
functions as a buffer layer for maintaining both crystallinity at an interface between an emitter and a base and p-n junction in well condition. Thereafter, polysilicon having grown on the silicon dioxide film
3
are removed by means of photolithography and anisotropic etching such as CF
4
gas etching.
Then, as illustrated in
FIG. 1B
, a silicon dioxide film
6
and further a silicon nitride film
7
are formed on the P
−
MBE layer
5
and the silicon dioxide film
3
by chemical vapor deposition (CVD). The silicon dioxide film
6
and the silicon nitride film
7
both have a thickness of about 100 nm. Then, a photoresist
8
is deposited over the silicon nitride film
7
, and patterned by photolithography, followed by anisotropic etching to thereby open an emitter region E.
Then, as illustrated in
FIG. 1C
, silicon and antimony are evaporated in the MBE apparatus to thereby deposit heavily doped amorphous silicon on the silicon substrate
1
at room temperature, followed by solid phase epitaxy at growth temperature of 730° C. to thereby form an N+ MBE layer
9
having a thickness in the range of 100 to 200 nm. Then, photolithography and subsequently anisotropic etching such as (CF
4
+O
2
) gas etching are carried out to the N+ MBE layer
9
to thereby form an emitter contact
9
a.
The thus obtained emitter contact
9
a
composed of the N+ MBE layer
9
has been already sufficiently activated. Thus, it is no longer necessary to carry out thermal annealing at high temperature above growth temperature, resulting in that impurities depth profile is scarcely varied, and that it is possible to obtain desired characteristics by controlling thickness of base and emitter and/or carrier concentration.
Thereafter, the photoresist
8
is patterned by photolithography and anisotropically etched to thereby open a base contact B.
Then, as illustrated in
FIG. 1D
, a titanium (Ti)/platinum (Pt) layer
10
is deposited all over a resultant by vacuum evaporation. A gold layer
11
is deposited on the Ti/Pt layer
10
, and then patterned by photolithography. The Ti/Pt layer
10
is anisotropically etched using the patterned gold layer
11
as a mask, to thereby form electrodes of base and emitter of a silicon bipolar transistor.
The above mentioned conventional method has an advantage that an emitter region almost free of crystal defects can be obtained without carrying out thermal annealing at high temperature for activation, because the thin base layer
4
is grown by MBE, and further the N+ MBE layer
9
is grown through solid phase epitaxy process by means of the MBE apparatus. To the contrary, the above mentioned conventional method has many shortcomings.
First, the emitter region is insufficiently shallow in depth, because the emitter region is established only through annealing in solid phase epitaxy.
Secondly, since a diffusion coefficient of boron in the base layer is greater than a diffusion coefficient of antimony in an emitter, a p-n junction interfacial plane between an emitter and a base is almost equal to an epi-poly interfacial plane established through the solid phase epitaxy. As a result, it is impossible to obtain sufficient crystallinity, which causes a base leakage current to be increased, thereby DC characteristic being deteriorated at a low current. As one of evidences for such deterioration,
FIG. 2
shows Gummel plots for a transistor fabricated in accordance with the above mentioned conventional method. It is understood in view of the two curves Ic and I
B
in
FIG. 2
that a base current IB is greater than a collector current Ic in the range where a current is small, resulting in that the forward current gain linearity is deteriorated.
Thirdly, a rapid thermal annealing (RTA) apparatus may be used in the conventional method to carry out implantation for forming a shallow emitter region. However, annealing is carried out in so short period of time that temperature in a wafer is not uniformized. As a result, there is generated dispersion in characteristics, which lowers a production yield.
Ion implantation and thermal diffusion, which have been widely used, have a shortcoming that they make the implantation depth so deep that crystal defects are increased, resulting in that it is necessary to carry out thermal annealing at high temperature for activation. In addition, those prior methods have another shortcoming that a silicon wafer has to be taken out of an MBE apparatus each time when ion implantation is to be carried out.
A report No. 27a-T-9 by the title of “B and Sb Heavy Doping for Si-MBE” in the 51st Applied Physical Society lecture meeting, Vol. 1, pp 239, Autumn 1990, has indicated a problem that it is impossible in conventional methods of fabricating a bipolar transistor to have steep impurities depth profile, because base and emitter are formed by ion implantation and thermal treatment at high temperature such as annealing. Recently, Si-MBE has been applied to formation of a thin base layer for establishing steep impurities depth profile at ambient temperature. However, technique for heavily doping B and Sb is not established yet. Thus, the results of the experiments are reported about activation rate, crystallinity, and dependency on azimuth of substrate planes during B and Sb are being heavily doped.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device and a method of fabricating the same which are capable of forming an emitter region which are shallow, but sufficiently uniform in impurities concentration with the result of no necessity of thermal annealing at high temperature after the formation of a base layer, prevention of degradation of crystallinity, and prevention of variation of impurities depth profile.
In one aspect, there is provided a method of fabricating a semiconductor device, including the steps of (a) forming a first molecular beam epitaxy layer on a semiconductor substrate, (b) implanting impurities into the first molecular beam epitaxy layer, and (c) forming a second mol
Lattin Christopher
NEC Compound Semiconductor Devices Ltd.
Niebling John F.
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