Active solid-state devices (e.g. – transistors – solid-state diode – Encapsulated
Reexamination Certificate
2001-04-27
2003-09-16
Cuneo, Kamand (Department: 2829)
Active solid-state devices (e.g., transistors, solid-state diode
Encapsulated
C257S686000, C257S777000, C438S127000
Reexamination Certificate
active
06621172
ABSTRACT:
Japanese patent application No.11-249702, filed Sep. 3, 1999 is hereby incorporated by reference in its entirety. International application con. of No. PCT/JP00/05954, filed Sep. 1, 2000, is hereby incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same, a circuit board, and electronic equipment.
2. Description of Related Art
Accompanied by miniaturization of electronic equipment, multichip modules including a plurality of semiconductor chips at high density have been developed. A stacked-CSP (Chip Scale/Size Package) in which multiple semiconductor chips are stacked in a single package is known as one type of multichip module.
For example, Japanese Patent Application Laid-open No. 9-260441 discloses a single packaged semiconductor device including a first semiconductor chip and a second semiconductor chip of a larger size than the first semiconductor chip which is mounted on the first semiconductor chip. According to this semiconductor device, since the first semiconductor chip located on the lower side is unstable, it may be difficult to wire bond the semiconductor chip located on the upper side.
SUMMARY OF THE INVENTION
A semiconductor device according to one aspect of the present invention comprises:
a first semiconductor chip which has a surface having a plurality of electrodes and is mounted on a substrate having an interconnect pattern, wherein the surface having the electrodes faces the substrate and the electrodes are electrically connected to the interconnect pattern;
a second semiconductor chip which has a surface having a plurality of electrodes and is mounted on the first semiconductor chip, wherein the surface of the second semiconductor chip having the electrodes opposes the first semiconductor chip and the electrodes of the second semiconductor chip are electrically connected to the interconnect pattern through wires;
a first resin provided between the substrate and the first semiconductor chip; and
a second resin, differing from the first resin, which seals the first and second semiconductor chips to the substrate.
According to this semiconductor device, the first resin provided between the first semiconductor chip and the substrate has properties differing from the second resin which seals the first and second semiconductor chips. This enables the first resin and the second resin to be selected so as to have properties suitable for each member to which the first resin and the second resin adhere. Therefore, it becomes possible to cope with ultrasonic vibration applied when wire bonding the second semiconductor chip by selecting the first resin, for example. Because of this, reliable wire bonding can be performed, whereby the semiconductor device can be obtained at high yield.
Note that the first and second semiconductor chips refer to two arbitrary semiconductor chips. The present invention is not limited to only two semiconductor chips but can be applied to more than two semiconductor chips.
A circuit board according to another aspect of the present invention is equipped with the above-described semiconductor device.
Electronic equipment according to still another aspect of the present invention comprises the above-described semiconductor device.
A method of fabricating a semiconductor device according to further aspect of the present invention comprises the steps of:
face-down bonding a first semiconductor chip to a substrate on which an interconnect pattern is formed;
mounting a second semiconductor chip on the first semiconductor chip;
electrically connecting the second semiconductor chip to the interconnect pattern through wires;
providing a first resin between the first semiconductor chip and the substrate; and
sealing the first and second semiconductor chips with a second resin which differs from the first resin.
According to this method, the first resin provided between the first semiconductor chip and the substrate has properties differing from those of the second resin with which the first and second semiconductor chips are sealed. This enables the first resin and the second resin to be selected so as to have properties suitable for each member to which the first resin and the second resin adhere. Therefore, it becomes possible to cope with ultrasonic vibration applied when wire bonding the second semiconductor chip by selecting the first resin, for example. Because of this, reliable wire bonding can be performed, whereby the semiconductor device can be fabricated at high yield.
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Abe Takashi
Nakayama Hirohisa
Nakayama Toshinori
Taniguchi Jun
Cuneo Kamand
Geyer Scott B.
Oliff & Berridg,e PLC
Seiko Epson Corporation
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