Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2008-10-14
2010-12-28
Purvis, Sue (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S787000, C257SE23010, C257SE21214, C438S460000
Reexamination Certificate
active
07859097
ABSTRACT:
A semiconductor device including a semiconductor chip having external connecting terminals formed on one side is restrained to cause chipping in ridge line portion of semiconductor chip. A cover layer103is formed on the other side of the semiconductor chip102. At least a part of an end portion106of the cover layer is outside of the ridge line portion107of the semiconductor chip.
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patent: 2007/0108636 (2007-05-01), Andoh
patent: 2007/0278678 (2007-12-01), Uchida
patent: 2001-230224 (2001-08-01), None
patent: 2006-80284 (2006-03-01), None
McGinn Intellectual Property Law Group PLLC
Moore Whitney
Purvis Sue
Renesas Electronics Corporation
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