Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2005-01-11
2005-01-11
Abraham, Fetsum (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S208000, C257S211000, C257S207000, C438S618000
Reexamination Certificate
active
06841880
ABSTRACT:
In the semiconductor device of the present invention, a plurality of dummy patterns are formed in a grid arrangement in the scribe line areas of a wafer, and a plurality of dummy patterns are formed in a diagonally forward skipped arrangement in the chip interior areas of the wafer. Altering the arrangement of dummy patterns in the chip interior areas and scribe line areas in this way enables formation of dummy patterns with greater uniformity in the chip interior areas and enables formation of dummy patterns with greater resistance to loss that occurs when dicing in scribe line areas.
REFERENCES:
patent: 6528818 (2003-03-01), Satya et al.
patent: 6614120 (2003-09-01), Sato et al.
patent: 2000-286263 (2000-10-01), None
patent: 3128205 (2000-11-01), None
patent: 2001-203261 (2001-07-01), None
patent: 2002-208676 (2002-07-01), None
Fukase Tadashi
Iguchi Manabu
Matsumoto Akira
Abraham Fetsum
NEC Electronics Corporation
Young & Thompson
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