Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-09-28
2003-05-27
Phan, Trong (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185270, C365S185290
Reexamination Certificate
active
06570788
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having a non-volatile memory transistor with a gate electrode stacked on a semiconductor substrate or well via an insulating film including an charge storing means therein and a semiconductor device provided with a logic circuit block and a memory block together.
Also, the present invention relates to a method of driving and method of producing the semiconductor device.
2. Description of the Related Art
In non-volatile memory devices, there are known a floating gate (FG) type, a metal-oxide-nitride-oxide-semiconductor (MONOS) type, a metal-nitride-oxide-semiconductor (MNOS) type, etc. corresponding to the types of charge storing means and stacked structure of the insulating film including the charge storing means in the memory transistor.
In a non-volatile memory transistor of the FG type, a floating gate comprised of polyorystalline silicon etc. is stacked on a semiconductor substrate or well via an insulating film, and, further, a control gate is stacked on the floating gate via an inter-gate insulating film comprised for example of an oxide-nitride-oxide (ONO) film.
In a non-volatile memory transistor of the MONOS type, a tunnel insulating film comprised for example of a silicon oxide film or nitrided oxide film, an interlayer insulating film comprised of a nitride film or an oxynitride film, and a top insulating film comprised of a silicon oxide film are stacked in that order on a semiconductor substrate or well, and a gate electrode is formed on the top insulating film.
On the other hand, non-volatile memory devices may be roughly divided by type of memory cell array into a NAND type and an NOR type.
In NAND type non-volatile memory devices, a write and erase operation are currently mainly performed by applying a high voltage between the semiconductor substrate or well and the gate electrode and utilizing Fowler Nordheim (FN) tunneling on the entire surface of the channel.
FIGS. 17A and 17B
schematically show a general method for setting the bias of an FG type memory transistor at the time of a write operation and an erase operation.
At the time of a write operation shown in
FIG. 17A
, a write voltage V′
pp
is applied to a control gate CG in a state where the semiconductor substrate or well is held at the ground potential. At this time, a source impurity region and drain impurity region are both held at the ground potential.
As a result, a high electric field is applied to the semiconductor substrate or well, so an inversion layer (channel) is formed in its surface portion, and electrons are injected in the floating gate FG by tunneling through the gate insulating film on the entire surface of the channel. When electrons are sufficiently injected into the floating gate FG, the memory transistor shifts from the erase state of a low threshold voltage to the write state of a high threshold voltage.
On the other hand, at the time of an erase operation shown in
FIG. 17B
, an erase voltage V
pp
′ is applied to the semiconductor substrate or well in a state where the control gate CG is grounded. At this time, the source impurity region and the drain impurity region are both held in a floating state.
As a result, electrons stored in the floating gate FG are withdrawn to the semiconductor substrate or well at the entire channel surface, and the memory transistor shifts to the erase state of a low threshold voltage.
The write and erase methods are basically the same regardless of differences in the types of charge storing means or memory cell arrays when performed over the entire channel surface.
Note that while about 8 nm is considered to be the limit in the FG type for reducing the thickness of a tunnel insulating film from the viewpoint of mainly the deterioration of the charge holding characteristic, in the MONOS type etc. where the charge storing means are made disperse, the data holding characteristic is excellent and the tunnel insulating film can be made thinner. Therefore, while the write or erase voltage is about 20V in the FG type, it can be reduced down to close to 10V in the MONOS type.
Note that in a so-called AND type, one type of NOR type, although there is a slight difference of grounding or leaving open the source and drain impurity regions, the write or erase operation is basically performed in the same way as in
FIGS. 17A and 17B
.
For this write or erase operation, a booster circuit for boosting an external power source voltage to generate a write voltage V
pp
or erase voltage V
pp
′ is provided in the non-volatile memory device.
Summarizing the problems to be solved by the invention, in non-volatile memory devices of the related art using the above write and erase method, however, although there is the advantage that the booster circuit can be made configured simply since boosting a negative voltage is unnecessary, a transistor with a high breakdown voltage specification, called a V
pp
-type transistor, is necessary. Therefore, at the present time, the production process is complex and progress cannot be made in reducing costs.
For example, an output transistor etc. of a circuit for driving a word line potential or well potential has to switch between the full range of a high voltage V
pp
or V
pp
′ at the time of a write or erase operation. Thus, a V
pp
-type transistor has to be used.
Compared with a memory transistor, V
cc
-type (external power source voltage using type) transistor, etc., a V
pp
-type transistor has a large gate length and gate insulating film thickness in accordance with the required breakdown voltage and is set to a large gate width in proportion to the gate length to obtain the necessary drive ability.
Also, the source and drain impurity regions have to be set deeper compared with a memory transistor or V
cc
-type transistor.
Further, frequent use is made of a structure, called an “offset structure”, where high concentration source and drain impurity regions are formed away from the gate end.
Therefore, the area occupied by the transistor is large and a special process not included in the production of a memory transistor or V
cc
-type transistor becomes required. This has become a major factor behind why not much progress can be made in reducing the costs of non-volatile memory transistors.
On the other hand, in so-called system LSIs etc., there has recently been active development of semiconductor devices embedded logic circuit blocks and memory blocks.
Since there are a large number of transistors and the operating speed is considered important in a logic circuit block, a V
cc
-type high speed transistor formed at the limit resolution of patterning in the same way as a memory transistor and formed with a thin gate insulating film is used as the transistor for the logic operations.
In such LSIs, transistors are optimized in the logic circuit block to make the area as small as possible. On the other hand, it is necessary to separately form three types of gate insulating films in the wafer, that is, for memory transistor use, high voltage use, and low voltage use, so the production process becomes further complex.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device increased in the degree of compatibility of production processes among different kinds of transistors and thereby able to be reduced in cost, a method of driving and method of producing the same.
According to a first aspect of the present invention, there is provided a semiconductor device comprising a memory transistor formed by stacking a gate electrode on a semiconductor substrate or a well via an insulating film including a charge storing means therein; and a write and erase circuit for supplying a write voltage or an erase voltage between said gate electrode and said semiconductor substrate or well at the time of a write or erase operation on the memory transistor; wherein said write and erase circuit comprises; a first voltage supply circuit for dividing said write voltage to a first and
Depke Robert J.
Holland & Knight LLC
Phan Trong
LandOfFree
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