Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With semiconductor element forming part
Reexamination Certificate
2001-02-20
2003-05-06
Fourson, George (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With semiconductor element forming part
C257S723000, C257S724000, C257S777000
Reexamination Certificate
active
06559528
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device provided with semiconductor elements and to a method for the fabrication of such a semiconductor device. The present invention relates more particularly to a semiconductor device protecting its semiconductor elements and securing establishment of electrical connections between the semiconductor elements and external equipment.
In recent years, since electronic equipment is becoming smaller and smaller in size and being highly improved in function, there have been strong demands for improvement in packaging density as well as the miniaturization and the high operation rate of the semiconductor device. In order to meet these demands, various forms of packaging have been developed. For example, the COC (Chip On Chip) module has been developed as a packaging form (Japanese Unexamined Patent Gazette No. H10-32307).
Hereinafter, a semiconductor device of a conventional COC module (hereinafter referred to as the “COC”) and a method for the fabrication of such a COC will be described with reference to FIG.
5
.
FIG. 5
schematically shows a cross section of the conventional COC
100
. The COC
100
includes a first semiconductor chip
101
containing a first semiconductor integrated circuit part and a second semiconductor chip
102
containing a second semiconductor integrated circuit part. These first and second semiconductor chips
101
and
102
are electrically connected together by a face-down technique. Since the face-down technique is used, the major surface of the semiconductor chip
102
faces downward while the backside surface of the semiconductor chip
102
faces upward.
The first semiconductor chip
101
is mounted on a die pad
106
a
of a lead frame
106
, and the second semiconductor chip
102
, located above the first semiconductor chip
101
, is smaller in chip size than the first semiconductor chip
101
. Both the first semiconductor chip
101
and the second semiconductor chip
102
are encapsulated with an encapsulating resin
108
.
Formed on the major surface of the first semiconductor chip
101
are a plurality of first element electrodes
103
electrically connected to the first semiconductor integrated circuit part. On the other hand, formed on the major surface of the second semiconductor chip
102
are a plurality of second element electrodes
104
electrically connected to the second semiconductor integrated circuit part. The first semiconductor chip
101
and the second semiconductor chip
102
are placed such that their major surfaces face each other, and a portion
103
a
of the first element electrodes
103
of the first semiconductor chip
101
and the second element electrodes
104
of the second semiconductor chip
102
are connected together electrically by a connection member (for example, a bump)
105
. Further, a portion
103
b
of the first element electrodes
103
of the first semiconductor chip
101
is electrically connected to an external lead (an external electrode)
106
b
of the lead frame
106
by a boding wire (for example, a wire of Au).
Referring still to
FIG. 5
, a method for the fabrication of the conventional COC
100
will be described below.
First, the first semiconductor chip
101
and the second semiconductor chip
102
are prepared. Following this, the connection member
105
, made of solder or the like, is formed on each of the second element electrodes
104
of the second semiconductor chip
102
. Next, the second semiconductor chip
102
is mounted onto the first semiconductor chip
101
such that each of the second element electrodes
104
of the second semiconductor chip
102
is connected to each of the first element electrode portions
103
a
of the first semiconductor chip
101
through the connection member
105
. Then, the connection member
105
is melted, thereby electrically connecting together the second element electrodes
104
of the second semiconductor chip
102
and the first element electrode portions
103
a
of the first semiconductor chip
101
.
Next, the first semiconductor chip
101
is mounted onto the die pad
106
a
of the lead frame
106
. This is followed by wire bonding of electrically connecting together the first element electrode portion
103
b
of the first semiconductor chip
101
and the external lead
106
b
of the lead frame
106
by a bonding wire (for example, a wire of Au). Lastly, the fist semiconductor chip
101
, the second semiconductor chip
102
, the die pad
106
a
of the lead frame
106
, and a portion of the external lead
106
b
of the lead frame
106
are all encapsulated by the encapsulating resin
108
, and the COC
100
is obtained.
However, the conventional COC
100
has difficulties in being multipin-ized to a further extent. That is, in the COC
100
, external connection is established by the external lead
106
b
extracted from a lateral surface of the encapsulating resin (the package)
108
, which makes it difficult to further provide many external electrodes (external terminals). Furthermore, the external dimensions of the COC
100
are constrained by the package dimensions such as the size of the lead frame
106
. Therefore, it is difficult to reduce the size of the COC
100
.
Bearing in mind the above-described problems, the present invention was made. Accordingly, a major object of the present invention is to provide a semiconductor device capable of coping with multipin-ization and reducible in size and a method for the fabrication of such a semiconductor device.
SUMMARY OF THE INVENTION
The present invention provides, in order to achieve the aforesaid object, a semiconductor device which comprises (a) a first semiconductor element having a major surface on which a plurality of first element electrodes are disposed, (b) a second semiconductor element having a major surface on which a plurality of second element electrodes are disposed, the major surface of the second semiconductor element facing the major surface of the first semiconductor element, (c) a connection member electrically connecting together at least a portion of the plural first element electrodes of the first semiconductor element and at least a portion of the plural second element electrodes of the second semiconductor element, (d) an insulation layer coating the major surface of the first semiconductor element and a backside surface of the second semiconductor element, (e) an opening portion formed in the insulation layer and exposing at least a portion of the plural first element electrodes, (f) a wiring layer formed on the insulation layer and electrically connected to the first element electrode exposed in the opening portion, and (g) a plurality of external electrodes formed, as portions of the wiring layer, on the insulation layer and electrically connectable to external equipment.
In an embodiment of the present invention, the first semiconductor element and the second semiconductor element are a semiconductor chip, respectively, and the area of the major surface of the first semiconductor element is greater than the area of the major surface of the second semiconductor element. Further, in an embodiment of the present invention, the first semiconductor element is a semiconductor chip formed in a semiconductor wafer.
It is preferable that at least a portion of the plural external electrodes is formed on the insulation layer located over the backside surface of the second semiconductor element.
In an embodiment of the present invention, the second semiconductor element has on its backside surface at least one external electrode electrically connectable to external equipment.
The semiconductor device of the present invention may further comprise a passivation film formed on the major surface of the first semiconductor element and having opening portions exposing the plural first element electrodes, wherein the insulation layer is formed on the passivation film.
The semiconductor device of the present invention may further comprise metal balls provided on the external electrodes.
The present invention provide
Fujimoto Hiroaki
Kaino Kazuyuki
Kumakawa Takahiro
Nakamura Yoshifumi
Sahara Ryuichi
Fourson George
Matsushita Electric - Industrial Co., Ltd.
Nixon & Peabody LLP
Studebaker Donald R.
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