Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2001-10-29
2003-01-28
Clark, Jasmine J B (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S781000, C257S784000, C257S774000, C257S758000
Reexamination Certificate
active
06512298
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a method for producing the same that has a built-in integrated circuit section used for information communication equipment or electronic equipment for offices and allows a high-density packaging provided with wires or electrodes that connect the semiconductor integrated circuit section to the terminals of external equipment.
Recently, with compactness, high density and high functionality of electronic equipment, compactness and high density have been required for semiconductor devices. To satisfy this need, a technique to form CSP (chip size package) within semiconductor wafers has come to be used (Japanese Laid-Open Patent Publication No. 8-102466). The CSP formed within a semiconductor wafer is called a wafer level CSP even after a semiconductor wafer is divided into chips.
Hereinafter, a conventional semiconductor device and a production method thereof will be described in detail in reference with the accompanying drawings.
FIG. 5
is a cross-sectional view of a conventional semiconductor device, more specifically, a conventional wafer level CSP.
As shown in
FIG. 5
, in the conventional wafer level CSP, a plurality of element electrodes
101
that are electrically connected to semiconductor elements are formed on a semiconductor wafer
100
in which the semiconductor elements are arranged in respective semiconductor chip forming regions (not shown). The surface of the semiconductor wafer
100
is covered with a passivation film
102
in which a plurality of openings
102
a
are arranged in order to expose the element electrodes
101
. On the passivation film
102
, a plurality of Cu wires
103
that are connected to the element electrodes
101
via the openings
102
a
are formed. The surface of each of the Cu wires
103
is covered with a Ni-plated layer
104
. On the passivation film
102
, a cover coating film (protective film)
105
is formed so as to cover the Cu wires
103
as well as Ni-plated layer
104
. In the cover coating film
105
, a plurality of openings
105
a
are formed so as to expose a plurality of external electrodes
106
that are formed of a portion of the Cu wires
103
(including the Ni-plated layer
104
) and are two-dimensionally arranged. A plurality of solder bumps
107
connected to the external electrodes
106
via the openings
105
a
are formed immediately above the external electrodes
106
as external electrode terminals.
The outline of a method for producing the conventional wafer level CSP is as follows.
First, a passivation film
102
is formed by spin-coating on the whole surface of the semiconductor wafer
100
provided with semiconductor elements and a plurality of element electrodes
101
electrically connected to the semiconductor elements in respective semiconductor chip forming regions. Then, a plurality of openings
102
a
is formed in the passivation film
102
so as to expose the element electrodes
101
by well-known techniques of photolithography and etching.
Next, a plurality of Cu wires
103
are formed on the semiconductor wafer
100
via the passivation film
102
so as to extend within the inner portion of respective semiconductor chip forming regions and to be connected to the element electrodes
101
via the openings
102
a
. Thereafter, a Ni-plated layer
104
is formed on the Cu wires
103
by electroless plating.
Then, a cover coating film
105
is formed so as to cover the Cu wires
103
, and then a plurality of openings
105
a
are formed on the cover coating film
105
in order to expose a plurality of external electrodes
106
that are formed of a portion of the Cu wires
103
and arranged two-dimensionally by well-known techniques of photolithography and etching. Thereafter, a plurality of solder bumps
107
that are connected to the external electrodes
106
via the openings
105
a
are formed immediately above the external electrodes
106
as external electrode terminals.
As described above, according to the wafer level CSP that is a conventional semiconductor device, the external electrodes
106
that are connected to the respective element electrodes
101
can be arranged two-dimensionally regardless of the arrangement of the element electrodes
101
, so that compact semiconductor device can be produced, and therefore, equipment such as information communication equipment can also be made small in size.
However, in the conventional semiconductor device, there exists a resistance in the wires connecting the element electrodes to the external electrodes (for example, Cu wires) in addition to a resistance in the wires connecting the semiconductor elements to the element electrodes (for example, Al wires). Because of the resistance, signal delay is increased and the problem is caused that high-speed transmission of signals between the semiconductor device and external equipment becomes difficult.
SUMMARY OF THE INVENTION
Therefore, with the foregoing in mind, it is an object of the present invention to provide a semiconductor device that allows high-speed transmission of signals between the semiconductor device and external equipment while compactness is achieved.
In order to achieve the above object, a semiconductor device of the present invention includes a semiconductor substrate provided with at least one semiconductor element, a first element electrode and a second element electrode formed on the semiconductor substrate and connected electrically to the semiconductor element, an insulating film formed so as to cover the first element electrode and the second element electrode, a first opening formed on the insulating film and exposing at least one portion of the first element electrode, a second opening formed on the insulating film and exposing at least one portion of the second element electrode, a first external electrode formed immediately above the first element electrode and connected to the first element electrode via the first opening, a second external electrode formed on the insulating film and a connecting wire formed on the insulating film and having one end connected to the second element electrode via the second opening and the other end connected to the second external electrode.
The semiconductor device of the present invention includes a first external electrode formed immediately above the first element electrode and connected to the first element electrode. Therefore, the first element electrode and the first external electrode are connected without a wire, so that the resistance between the first element electrode and the first external electrode can be reduced and signal delay can be decreased. Thus, high-speed transmission of signals between the semiconductor device and external equipment becomes possible.
The semiconductor device of the present invention includes a second external electrode formed on the insulating film on the semiconductor substrate and a connecting wire formed on the insulating film and having one end connected to the second element electrode and the other end connected to the second external electrode. Therefore, regardless of the arrangement of the second element electrodes, the second external electrodes electrically connected to the second element electrodes can be arranged two-dimensionally, so that it is possible to provide multiple external electrode terminals in a small area. As a result, it becomes possible to realize a compact semiconductor device that is capable of including multiple pins.
Furthermore, according to the semiconductor device of the present invention, the first external electrode, the second external electrode and the connecting wire can be formed easily by patterning a conductive film formed on the semiconductor substrate to integrally form the first external electrode, the second external electrode and the connecting wire. Therefore, manufacturing cost can be reduced.
In the semiconductor device of the present invention, the semiconductor substrate may be a semiconductor wafer or a chip obtained by dividing a semiconductor wafer.
In the semiconduct
Kainoh Kazuyuki
Kumakawa Takahiro
Sahara Ryuichi
Shimoishizaka Nozomi
Watase Kazumi
Clark Jasmine J B
Matsushita Electric - Industrial Co., Ltd.
Nixon & Peabody LLP
Studebaker Donald R.
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