Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – For plural devices
Reexamination Certificate
2000-03-20
2001-04-10
Lee, Eddie C. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
For plural devices
C174S050510, C257S685000, C257S686000, C257S725000, C257S758000
Reexamination Certificate
active
06215182
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor devices and methods for producing the same, and more particularly to a semiconductor device and a method for producing the semiconductor device, which is configured to have a plurality of semiconductor elements stacked therein.
In recent years, with increasing demand for miniaturized portable equipment such as a portable telephone, a semiconductor device, which is carried therein, has also been required to become smaller. In order to support this situation, a stack-type semiconductor device, which has a plurality of semiconductor elements stacked within resin for encapsulation (a package) thereof, is developed.
2. Description of the Related Art
FIGS. 1 and 2
show a conventional stack-type semiconductor device
1
A which comprises a plurality of leads
5
serving as connecting terminals.
FIG. 1
is a cross-sectional view of the semiconductor device
1
A and
FIG. 2
is plan view of the semiconductor device
1
A where encapsulating resin
6
A is partly removed.
The semiconductor device
1
A shown in
FIGS. 1 and 2
is configured to have three semiconductor elements
2
,
3
and
4
which are stacked on a stage portion
5
a
provided on the leads
5
. On the semiconductor elements
2
,
3
and
4
, there are respectively provided first electrodes
7
, second electrodes
8
and third electrodes
9
, which are connected to bonding-pads
5
c
of the leads
5
via first wires
10
, second wires
11
and third wires
12
, respectively. Also, outer leads
5
b
of the leads
5
are formed extending to the outside thereof, for example, like a gull wing.
Since the semiconductor device
1
A shown in
FIGS. 1 and 2
is configured such that the outer leads
5
b
extend out of the encapsulating resin
6
A and the bonding-pads
5
c
to which the wires
10
through
12
are joined are formed outside the semiconductor elements
2
through
4
, this results in a large size of the semiconductor device
1
A. Further, although the semiconductor device
1
A has a multi-pin structure resulting from the high-density and stack of the semiconductor elements
2
through
4
, there is a limit to shortening pitches of the adjacent leads
5
and this also results in the large size of the semiconductor device
1
A.
On the other hand,
FIGS. 3 and 4
show a conventional BGA-type (ball grid array type) semiconductor device
1
B which has a plurality of solder balls
15
serving as connecting terminals.
FIG. 3
is a cross-sectional view of the semiconductor device
1
B and
FIG. 4
is a plan view of the semiconductor device
1
B where the encapsulating resin
6
B is partly removed. In addition, in
FIGS. 3 and 4
, parts, which are the same as those shown in
FIGS. 1 and 2
, are given the same reference numerals.
The BGA-type semiconductor device
1
B is configured to have first, second and third semiconductor elements
2
,
3
and
4
which are stacked on a substrate
13
thereof, for example, a printed wiring substrate. On the semiconductor elements
2
.
3
and
4
, there are respectively provided electrodes
7
,
8
and
9
. These electrodes
7
through
9
, using first, second and third wires
10
,
11
and
12
respectively, are connected to a plurality of bonding pads
14
which is formed on the substrate
13
where the semiconductor elements
2
through
4
are stacked.
The plurality of bonding pads
14
are connected to the respective solder balls
15
via through-holes and wires (both not shown). Thus, each of the semiconductor elements
2
,
3
and
4
is connected to the solder balls
15
via the wires
10
through
12
, the bonding pads
14
, the not-shown through-holes and wires.
As previously described, since the BGA-type semiconductor device
1
B is configured such that the solder balls
15
serving as connecting terminals are provided under the stacked semiconductor elements
2
through
4
, it can be produced smaller in size than the semiconductor device
1
A of
FIGS. 1 and 2
. Further, since the adjacent pitches of the bonding pads
14
can be designed narrower than those of the leads
5
shown in
FIGS. 1 and 2
, the bonding pads
14
can support the multi-pin structure.
As can be seen from
FIGS. 1 through 4
, however, either in the semiconductor devices
1
A or
1
B, since the leads
5
or the bonding pads
14
are connected to the semiconductor elements
2
,
3
and
4
by using the wires
10
,
11
and
12
, it is imperative that the wires
10
,
11
and
12
be laid within the encapsulating resin
6
A or
6
B.
Particularly, in the semiconductor device
1
A or
1
B where the semiconductor elements
2
through
4
are stacked, the first wires
10
need to be laid long enough so that the uppermost-positioned semiconductor element
2
can be connected to the leads
5
or the bonding pads
14
. Thereby loop heights of the first wires
10
(heights from the leads
5
or the bonding pads
14
to the first wires
10
) become high and this results in a large size (particularly, in height) of the semiconductor device
1
A or
1
B.
In order to solve the above mentioned problems and miniaturize the semiconductor devices
1
A and
1
B, it is necessary to lower the wires
10
through
12
. Lowering the wires
10
through
12
, however, brings about a problem that wires
10
through
12
may contact corner portions of the semiconductor elements
2
through
4
, or adjacent wires thereof may contact each other to generate a short-circuit. As a result, reliability of the semiconductor device
1
A or
1
B is degraded.
SUMMARY OF THE INVENTION
It is a general object of the present invention to provide a semiconductor device and a method for producing the same, in which the above disadvantages are eliminated.
Another and a more specific object of the present invention is to provide a semiconductor device comprising:
a plurality of semiconductor elements, at least including an uppermost one, a middle one, and a lowermost one, which are stacked on a substrate;
a plurality of wires, each being electrically connected between two of electrodes, respectively provided on two adjacent ones of the plurality of semiconductor elements, or between two ones of electrodes, respectively provided on said substrate and said lowermost semiconductor element which is directly stacked on said substrate; and
a plurality of spacer members, respectively provided between said wires and said electrodes provided on the semiconductor elements other than said uppermost one; wherein
space is formed between said wires and the plurality of semiconductor elements by said spacer members, without contact therebetween.
Still another object of the present invention is to provide a method for producing a semiconductor device, comprising the steps of:
(a) stacking a plurality of semiconductor elements, at least including an uppermost one, a middle one, and a lowermost one, on a substrate; and
(b) performing a wire bonding process in which a plurality of wires are each electrically connected between two of electrodes, respectively provided on two adjacent ones of the plurality of semiconductor elements, or between two electrodes, respectively provided on said substrate and said lowermost semiconductor element which is directly stacked on said substrate; wherein
said wire bonding process comprises:
(c) performing a spacer-member arranging process in which a plurality of spacer members are provided between said wires and said electrodes provided on the semiconductor elements other than said uppermost one; and
(d) performing a junction process in which said wires are respectively joined to said spacer members formed by said spacer-member arranging process.
Other objects, features and advantages of the present invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings.
REFERENCES:
patent: 5422435 (1995-06-01), Takiar et al.
patent: 6005778 (1999-12-01), Spielberger et al.
patent: 10-70232 (1998-03-01), None
Akashi Yuji
Hiraiwa Katsuro
Nomoto Ryuji
Okuda Hayato
Ozawa Kaname
Armstrong Westerman Hattori McLeland & Naughton LLP
Fujitsu Limited
Lee Eddie C.
Wilson Allan R.
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