Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
1999-10-05
2002-07-09
Clark, Jasmine J B (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S758000, C257S774000, C257S757000
Reexamination Certificate
active
06417565
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method for producing the same, more particularly relates to a semiconductor device having a conductive layer in which a work function of a conductive material located at a boundary with an insulating film formed on a substrate is controlled to near the substantial center of an energy band gap of a substrate material, that is, the “mid-gap”, and to a method for producing the same.
2. Description of the Related Art
In semiconductor devices in recent years, complete separation among elements has become easy by using a silicon-on-insulator or semiconductor-on-insulator (SOI) substrate as the substrate. Further, it is known that, if such an SOI substrate is used, the control of the latchup and the software error peculiar to a complementary metal oxide semiconductor (MOS) transistor (CMOSTr) becomes possible, so studies have been conducted on the increase of speed and increase of reliability of large-scale integrated circuits (LSIs) comprised of CMOSTrs using SOI substrates having silicon (Si) active layers of a thickness of about 500 nm from a relatively early stage.
Further, recently, it has been learned that if the Si active layer of the SOI substrate surface is made further thinner to about 100 nm and the impurity concentration of a channel region is controlled to be relatively low to make substantially the entire Si active layer depleted (make it a full depletion type), excellent characteristics such as suppression of a short channel effect and improvement of a current driving capability of the MOSTr are obtained.
On the other hand, as a gate electrode material, polycrystalline silicon doped with an n-type impurity (n
+
poly-Si) has been frequently used in the past. However, in order to set a threshold voltage (Vth) of an n-channel MOS transistor (NMOSTr) to near 0.5 to 1.0V of a usual enhancement type MOS transistor by using n
+
poly-Si for the gate electrode material, it is necessary to control the impurity concentration of the channel region to about 10
17
/cm
3
or more.
Further, in order to prepare a full depletion type enhancement type MOSTr, the method has been studied of using a polycrystalline silicon doped with boron as a p-type impurity (p
+
poly-Si) as the gate electrode material in place of the n
+
poly-Si for the gate electrodes of the NMOSTr.
In this method of using p
+
poly-Si for the gate electrodes of an NMOSTr, if the impurity is not included in the channel region (non-doped), Vth becomes substantially 1.0V. Further, where it is intended to make Vth a further lower value, it has been necessary to perform counter-doping to dope an n-type impurity, for example, phosphorus (P
+
), in the channel region of the NMOSTr. However, when performing the counter-doping, the short channel effect is increased, so this is not preferred for a miniaturized LSI.
In this way, in any case of using n
+
poly-Si and p
+
poly-Si as the gate electrode material, in the preparation of a semiconductor device using an SOI substrate having a fine structure with a thin silicon active layer, it was extremely difficult to control the Vth of a full depletion type MOSTr to a suitable value of about 0.5V.
Further, even in the case of preparing a MOSTr with a channel region of a partial depletion type, careless increase of the impurity concentration of the channel region is not preferred in that it increases the drain leak current.
Further, semiconductor devices using bulk silicon substrates have been being miniatured as well. When using a bulk silicon substrate, it is not possible to form a surface channel type MOSTr resistant to a short channel effect simultaneously in both of the N-channel and the P-channel using only n
+
poly-Si for the gate electrodes. Therefore, as shown in
FIGS. 1A
to
1
C, a so-called dual gate process of using n
+
poly-Si for the NMOSTrs (shown in
FIG. 1A
) and using p
+
poly-Si for the p-channel MOS transistors (PMOSTr) (shown in
FIG. 1B
) has been studied for the purpose of adjustment of the Vth by using the work function of the gate electrodes.
However, in this dual gate process as well, when using poly-Si gate electrodes
14
a
and
14
b
of different types of dopants between the NMOSTr (shown in
FIG. 1A
) and the PMOSTr (shown in FIG.
1
B), as shown in
FIG. 1C
, there is a problem that impurities in the gate electrodes diffuse into each other (indicated by arrows in the figure) in parts at which the n
+
poly-Si gates of the NMOSTr and the p
+
poly-Si gates of the PMOSTr are connected and that the work functions of the gate electrodes largely fluctuate.
This problem becomes particularly conspicuous when a silicide is further formed at an upper layer of the poly-Si to be made to tungsten polycide (W-polycide) in order to lower the resistance of the gate electrodes formed by the dual gate process, as shown in
FIGS. 1A
to
1
C, since the diffusion coefficient of the dopant in the tungsten silicide (WSi
x
) is extremely large.
Note that, in
FIGS. 1A
to
1
C,
11
denotes a silicon substrate,
12
a field oxide film,
13
a gate insulating film,
14
a
a gate electrode of a NMOS transistor,
14
b
a gate electrode of a PMOS transistor,
14
c
a junction portion of the gate electrodes of the NMOS transistor side and the PMOS transistor side, and
15
an inter-layer insulating film.
In this way, even in a case where a SOI substrate is used and even in a case where a bulk silicon substrate is used, in order to deal with the miniaturization of semiconductor devices in the future, there is a problem with usage of different types of poly-Si for the gate electrode material. In place of this, it has been considered necessary to use a gate electrode material having a work function near the mid-gap.
The energy band of the semiconductor has a structure where an electronically filled band (a filled band or a valence band) and an empty band (conduction band) are separated by a prohibit band, and in the present invention, a gate electrode material having a work function near the mid-gap means a conductive material which has a work function (energy difference between a vacuum level and a Fermi level) almost the same as that near the center (near mid-gap) of the width of this prohibit band (band gap).
Summarizing the problem to be solved by the invention, among the gate electrode materials having a work function near this mid-gap, refractory metal silicide or refractory metal does not directly react with the SiO
2
and does not cause conspicuous deterioration of the gate withstand voltage, so attracts attention as particularly preferred material and has been studied as gate electrode material.
However, as shown in
FIG. 2
, when a gate insulating film
23
is formed on a silicon substrate
21
and a gate electrode is further formed on this by a single layer film
24
made of WSi
x
or another refractory metal silicide, there is the problem that a reduction of the gate insulation withstand voltage or a reduction of a gate capacity occurs in comparison with the case of the related art where a gate electrode such as poly-Si (or W-polycide) is used. Note that, in
FIG. 2
,
21
denotes a silicon substrate,
22
a field oxide film,
23
a gate insulating film,
24
a gate electrode made of a single WSi
x
layer, and
25
an inter-layer insulating film.
The reduction of the gate insulation withstand voltage is not preferred for a next generation device which is further miniaturized and where the gate oxide film is made further thinner. Further, the reduction of the gate capacity invites a reduction of the drive capability of the transistors etc. and as a result ends up lowering the operating speed of the device.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device having a conductive layer, preferably a gate electrode, using a conductive material having a work function near the mid-gap of the energy band gap of the substrate material, preferably silicon, at le
Clark Jasmine J B
Kananen, Esq. Ronald P.
Rader & Fishman & Grauer, PLLC
Sony Corporation
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