Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
2001-04-13
2004-10-26
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S244000, C438S255000, C438S387000
Reexamination Certificate
active
06809001
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having a capacitor constituting a dynamic random access memory (DRAM) cell wherein the capacity of the capacitor is increased by roughening a surface of the cylindrical storage node, and a method for producing such semiconductor device.
2. Discussion of Background
FIG. 6
is a cross-sectional view of a conventional semiconductor device as disclosed in JP-A-9-186297.
FIG. 6
shows mainly the structure of a cylindrical capacitor in cross section, which constitutes a DRAM cell. In
FIG. 6
, reference numeral
101
designates a semiconductor substrate, numeral
101
a
designates a source/drain region as a transistor element formed in a surface region of the semiconductor substrate
101
, numeral
102
designates a device isolation oxide layer formed on the surface of the semiconductor substrate
101
, a numeral
103
designates a word line formed on the semiconductor substrate
101
through a gate insulating film, which constitutes a gate electrode of the transistor element, numeral
104
designates an interlayer insulating film formed on the transistor element, numeral
105
a
designates a cylindrical storage node formed in contact with a source/drain region
101
a
between adjacent source/drain regions, which is provided with a cylindrical portion extending upward at a position on the interlayer insulating film
104
, numeral
106
designates a dielectric film formed on the cylindrical storage node
105
a
, and numeral
107
designates a cell plate laminated to cover an outer surface of the dielectric film
106
. The cylindrical storage node
105
a
, the dielectric film
106
and the cell plate
107
constitute a cylindrical capacitor
108
.
In the conventional semiconductor device shown in
FIG. 6
, the surface area of the storage node is increased by forming a plurality of pin holes
105
aa
in a cylindrical portion of the cylindrical storage node
105
a.
A silicon layer constituting the cylindrical storage node
105
a
is formed by using a vapor-phase epitaxy method at a temperature which is higher than a temperature for forming an amorphous structure but lower than a temperature for forming a polycrystalline structure while an impurity gas is introduced therein.
However, since thus formed silicon layer has crystallized portions in it, that portions are easily etched earlier than the other portion. Under such circumstances, when an anisotropic etching is conducted to the silicon layer having locality crystallized portions, only the crystallized portions are selectively removed whereby pin holes
105
aa
are formed.
Another conventional technique for forming a roughened surface is disclosed in JP-A-7-74268.
FIG. 7
shows the structure of a semiconductor device in cross section formed by such technique.
In the cross-sectional view showing mainly the structure of a cylindrical storage node
105
b
, the cylindrical storage node
105
b
ham a cylindrical portion in which an inner wall and an upper surface of a bottom portion are roughened. Numeral
109
designates a bit line formed in contact with the other source/drain region
101
a
between the adjacent source/drain regions. Other reference numerals designate the same or corresponding part shown in FIG.
6
. The reason why an outer wall of the cylindrical portion of the cylindrical storage node
105
b
is not roughened in the semiconductor device shown in
FIG. 7
, is to eliminate a disadvantage that when a heat treatment is conducted with use of a silane gas to obtain a roughened surface, spherical silicon grains having a uniform grain size are formed in the outer wall, and short circuit between adjacent storage nodes are caused. Further, there is another disadvantage that the formation of the silicon grains having a uniform grain size influences the formation of the dielectric film
106
and the cell plate
107
which are conducted subsequently.
In the conventional semiconductor device shown in
FIG. 6
, some of the pin holes
105
aa
penetrate from the outer wall to the inner wall of the cylindrical portion of the cylindrical storage node
105
a
. In this case, a sufficient physical strength can not be assured for the cylindrical storage node
105
a
, and there causes the destruction or the breakage of the cylindrical portion in subsequent processes.
In the conventional semiconductor device shown in
FIG. 7
, it was difficult to control the size of the silicon grains formed to obtain a roughened surface, and scattering of the silicon grain size was large whereby it was difficult to form a roughened surface in the cylindrical portion of the cylindrical storage node
105
b.
It has been considered to control the scattering of the silicon grain size. With a demand of miniaturizing capacitor elements, the film thickness from the outer wall to the inner wall of the cylindrical portion has further been reduced. Under such circumstances, when both surfaces of the outer wall and the inner wall are to be roughened, silicon grains are entirely formed in the cylindrical portion whereby air gaps are resulted between adjacent silicon grains. In this case, the physical strength of the cylindrical portion can not be assured and there causes the destruction or the breakage of the cylindrical portion.
It has been considered to roughen both surfaces of the outer wall and the inner wall by controlling the grain size of the silicon grains to be mall. In this case, however, it is required to reduce the grain size of the silicon grains, and it is difficult to increase remarkably the surface area of the cylindrical portion.
SUMMARY OF THE INVENTION
It is an object of the invention to eliminate the above-mentioned disadvantages and to provide a semiconductor device having a cylindrical storage node which provides a sufficient physical strength and which increases the surface area by roughening the surface of the cylindrical portion.
In accordance with a first aspect of the invention, there is provided a semiconductor device which comprises a capacitor of a stacked structure including a cylindrical storage node, a dielectric film and a cell plate, wherein the storage node has a cylindrical portion and a bottom portion; an outer wall of the cylindrical portion which is in contact with the dielectric film has a roughened surface; and an inner wall of the cylindrical portion has a smoothed surface.
In a second aspect of the present invention, there is provided a semiconductor device according to the first aspect, wherein silicon grains are formed in the outer wall of the cylindrical portion to provide projections and recesses in the outer wall surface, and the inner wall is composed of amorphous silicon.
In a third aspect of the present invention, there is provided a semiconductor device according to the first aspect, wherein the dielectric film is formed on the outer wall, the inner wall and the bottom portion of the cylindrical storage node.
In a fourth aspect of the present invention, there is provided a semiconductor device according to the first aspect, wherein an insulating film is formed so as to be in contact with the inner wall and an upper surface of the bottom portion of the cylindrical portion of the cylindrical storage node, the insulating film constituting the core of the cylindrical portion, and the dielectric film is formed on the outer wall of the cylindrical portion.
In accordance with a fifth aspect of the present invention, there is provided a method for producing a semiconductor device having a cylindrical storage node comprising a bottom portion and a cylindrical portion which surrounds an outer circumference of the bottom portion and extends upward, which comprises a step of forming a contact hole which penetrates an interlayer insulating film formed on a semiconductor substrate; a step of forming an electric conductive film on the interlayer insulating film whereby the contact hole is filled to obtain a contact to the substrate; a step of forming an insulating film on the electric conductive film; a step of patterning
Mori Kiyoshi
Shirosaki Masami
Tsuchimoto Junichi
Fourson George
Maldonado Julio J.
Renesas Technology Corp.
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