Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With structure for mounting semiconductor chip to lead frame
Reexamination Certificate
2006-10-25
2009-08-25
Louie, Wai-Sing (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
With structure for mounting semiconductor chip to lead frame
C257SE23040
Reexamination Certificate
active
07579677
ABSTRACT:
In a power semiconductor device, a joint between the power semiconductor element and frame plated with Ni is composed of a laminated structure comprising, from the power semiconductor element side, an intermetallic compound layer having a melting point of 260° C. or higher, a Cu layer, a metal layer having a melting point of 260° C. or higher, a Cu layer and an intermetallic layer having a melting point of 260° C. or higher. The structure of the joint buffers the stress generated by the secondary mounting and temperature cycle at the bond for the semiconductor element and the frame having a large difference in thermal expansion coefficient from each other.
REFERENCES:
patent: 5465007 (1995-11-01), Ikeda et al.
patent: 6727587 (2004-04-01), Riedl
patent: 2005/0153532 (2005-07-01), Osenbach et al.
William W. So, et al., “High Temperature Joints Manufactured at Low Temperature”, Proceeding of Electrical and Computer Engineering, University of California, Irvine, CA 92697-2625, pp. 284-291, 1998.
Yamamoto, et al., “Reactivity to Form Intermetallic Compounds in the Micro Joint Using Sn-Ag Solder”, Abstract of MES 2003, Oct. 2004, p. 45.
Ikeda Osamu
Kagii Hidemasa
Nakamura Hiroyuki
Oka Hiroi
Okamoto Masahide
Antonelli, Terry Stout & Kraus, LLP.
Jahan Bilkis
Louie Wai-Sing
Renesas Technology Corp.
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