Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – And gettering of substrate
Reexamination Certificate
2000-03-06
2003-02-25
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
And gettering of substrate
C438S520000, C438S528000, C438S473000, C438S407000
Reexamination Certificate
active
06524928
ABSTRACT:
BACKGROUND
The present invention relates to a method of manufacturing a semiconductor device having an SOI substrate.
In a process of manufacturing a semiconductor device, a heavy metal pollution results in a junction leak and the deterioration of a withstand voltage of gate oxide film. Some gettering techniques are used to prevent the deterioration of the characteristics of the semiconductor device due to the heavy metal pollution. An intrinsic gettering technique, which utilizes the deposition of oxide included in a silicon wafer manufactured by a Czochralski (CZ) lifting method, is ordinarily used.
Oxide atoms, which are deposited by a heat treatment, form fine defects and integrated defects. These defects have the characteristics of forming a distorted field and easily adhering heavy metal impurity atoms. In the above-mentioned intrinsic gettering technique, an out diffusion reduces the concentration of the oxide on the surface of the wafer forming the element, and the oxide is deposited inside the wafer, thereby fixing the heavy metal.
On the other hand, there is an extrinsic gettering technique, which forms impurity diffusion layer, a polycrystal silicon, a damage layer and the like at the reverse side of the wafer, and forms a distorted field in this area to fix heavy metal impurity atoms.
Recently, a power IC and a high-speed operating LSI, in which a low voltage control circuit and a high voltage output circuit are formed in one chip, is formed on an SOI substrate that is effective for reducing an isolation area and parasitic effects. The SOI substrate is constructed in such a manner that a semiconductor layer is formed on a semiconductor substrate through an insulating film. If an oxide concentration of the semiconductor layer, in which elements are formed, is lowered to 5×10
17
atom/cm
−3
or less by a heat treatment during the process of manufacturing the SOI substrate, an oxide is not deposited in a second semiconductor layer. Thus, heavy metal is not fixed inside the semiconductor layer.
Since the insulating film is between the semiconductor layer and the semiconductor substrate, the formation of a defect layer and a high-concentration impurity diffused layer for gettering would achieve a smaller effect than in the case where a defect layer and a high-concentration impurity diffused layer for gettering is formed at the reverse side of a CZ wafer.
To solve this problem, a gettering layer is formed for gettering heavy metal in the semiconductor layer, as disclosed in, for example, Japanese Patent Provisional Publication No. 10-032209. In this method, a high-concentration impurity diffused layer is provided between the semiconductor layer and the insulating film, and the heavy metal is fixed in the impurity diffused layer. This method improves the electric characteristics of the semiconductor device such as the voltage characteristics.
In a high voltage semiconductor device formed on the SOI substrate, the semiconductor layer and the insulating film share an electric field. In the method disclosed by Japanese Patent Provisional Publication No. 10-032209, the high-concentration impurity diffused layer with a gettering effect stops the spread of a depletion layer and makes it impossible to spread the electric field up to the insulating film. Therefore, it is impossible to achieve the semiconductor device with a high withstand voltage according to this reference.
Japanese Patent Provisional Publication No. 61-32433 discloses a method comprising the step of implanting ions into a semiconductor layer to thereby selectively form defect regions. In this method, the ions implanted into the semiconductor layer are of the type that is normally not used in the manufacture of semiconductor devices. Such ions are difficult to handle and are not productive. Moreover, such ions have a lower gettering effect as compared with boron and the like.
Japanese Patent Provisional Publication No. 63-38235 specifically discloses a surface concentration of impurities in an impurity diffused region with a gettering effect.
It is therefore an object of the present invention to provide a high voltage semiconductor device, which reduces the size of semiconductor elements and has a region with a sufficient gettering effect, and a manufacturing method therefore.
SUMMARY OF THE INVENTION
The above object can be accomplished by providing is a semiconductor device, which is formed of an SOI (Silicon On Insulator) on which a semiconductor layer is formed on a semiconductor substrate through an insulating film, and in which semiconductor elements are formed in said semiconductor layer of said SOI substrate. The semiconductor device has an impurity diffused region with a surface concentration of between 1×10
18
atom/cm
−3
and 5×10
20
atom/cm
−3
formed around activation regions in which said semiconductor elements are formed. The impurity diffused region is preferably adjacent to activation regions or in close proximity to said activation regions.
The above object can also be accomplished by a method of manufacturing a semiconductor device comprising the steps of introducing impurities into said impurity diffused region before the formation of gate oxide films in said semiconductor elements having an MOS structure. After the formation of said semiconductor elements with the MOS structure, a surface concentration of said impurity diffused region is between 1×10
18
atom/cm
−3
and 5×10
20
atom/cm
−3
.
Preferably, the impurities forming said impurity diffused region are at least one of the following: boron, phosphorous, arsenic and fluorine. If plural kinds of impurities are mixed, a surface concentration of all the mixed impurities is preferably between 1×0
18
atom/cm
−3
and 5×10
20
atom/cm
−3
.
According to another aspect of the present invention, a method of manufacturing a semiconductor device, which is formed by an SOI (Silicon On Insulator) on which a semiconductor layer is formed on a semiconductor substrate through an insulating film, and in which semiconductor elements are formed in said semiconductor layer of said SOI substrate, includes the steps of: forming an impurity diffused region in advance in a region in which an isolation groove is formed, and forming said isolation groove through said impurity diffused region.
As stated above, the provision of the impurity diffused region for gettering in close proximity to the activation region efficiently performs the gettering of impurities such as heavy metal introduced into the activation region. Moreover, the formation of the impurity diffused region in the isolation groove forming region before the formation of the isolation groove reduces an area wasted by the impurity diffused region. This reduces the size of the semiconductor elements.
REFERENCES:
patent: 3897273 (1975-07-01), Marsh et al.
patent: 4796073 (1989-01-01), Bledsoe
patent: 5108783 (1992-04-01), Tanigawa et al.
patent: 6084248 (2000-07-01), Inoue
patent: 61-32433 (1986-02-01), None
patent: 362098620 (1987-05-01), None
patent: 63-38235 (1988-02-01), None
patent: 402170551 (1990-07-01), None
patent: 403034326 (1991-02-01), None
patent: 10-32209 (1998-02-01), None
Niebling John F.
Rossi & Associates
Simkovic Viktor
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