Active solid-state devices (e.g. – transistors – solid-state diode – Responsive to non-electrical signal – Electromagnetic or particle radiation
Reexamination Certificate
2001-01-17
2003-08-12
Chaudhuri, Olik (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Responsive to non-electrical signal
Electromagnetic or particle radiation
C257S501000, C257S534000, C257S623000
Reexamination Certificate
active
06605852
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device having an element isolation region and a method for manufacturing the same.
BACKGROUND
With the miniaturization of semiconductor devices (for example, MOS transistors) promoted in recent years, a further miniaturization of element isolation regions in semiconductor devices is required. In order to achieve a further miniaturization of element isolation regions in semiconductor devices, a trench isolation technique has been introduced. In the trench isolation technique, trenches are provided between semiconductor elements over a semiconductor substrate, and a dielectric material is filled in the trenches to isolate the semiconductor elements from one another. One example of the element isolation technique is described below.
FIG. 11
shows a silicon substrate
110
having trenches
116
, and a dielectric layer
121
formed over the silicon substrate
110
. A polishing stopper layer
114
is formed over effective convex regions
130
in the silicon substrate
110
. A pad layer
112
is interposed between the effective convex regions
130
and the polishing stopper layer
114
.
As shown in FIG.
11
(
b
), the dielectric layer
121
is planarized using the polishing stopper layer
114
as a stopper. The planarization of the dielectric layer
121
is performed by a chemical-mechanical polishing method (hereinafter referred to as a “CMP method”).
Then, as shown in FIG.
11
(
c
), the polishing stopper layer
114
is removed to thereby form trench dielectric layers
120
, whereby trench isolation regions
124
are completed.
However, as shown in FIG.
11
(
b
), a certain device design may require that plural effective convex regions
130
be closely formed in one area and an isolated effective convex region
130
is formed separated from such area. In this case, the following problems occur.
When the dielectric layer
121
is planarized by the CMP method, the polishing stopper layer
114
at the isolated effective convex region
130
may be excessively cut. On the other hand, the polishing stopper layer
114
over the mutually densely formed effective convex regions
130
may not be cut enough as compared to the polishing stopper layer
114
at the isolated effective convex region
130
. This phenomenon occurs because the polishing rate differs depending on pattern densities of the effective convex regions
130
. In other words, the polishing pressure is concentrated over the polishing stopper layer
114
at the isolated effective convex region
130
. As a result, the polishing rate at the isolated effective convex region
130
becomes greater than the polishing rate at the mutually densely formed effective convex regions
130
. Consequently, the polishing stopper layer
114
at the isolated effective convex region
130
is excessively polished.
When the polishing stopper layer
114
at the isolated effective convex region
130
is excessively polished, the thickness of the resultant trench dielectric layers
120
become irregular, as shown in FIG.
11
(
c
). Also, the polishing stopper layer
114
cannot properly perform its function. Moreover, as the isolated effective convex region
130
is excessively polished, the polishing cloth warps, and erosion occurs in the polishing stopper layer
114
in the area where the effective convex regions
130
are mutually densely formed. The erosion is a phenomenon in which a corner section
114
a
of the polishing stopper layer
114
is cut. Also, when the polishing cloth warps, dishing occurs in an upper portion of the dielectric layer
121
. The dishing is a phenomenon in which an upper portion of the dielectric layer
121
is formed in a dish shape.
In order to solve the problems described above, one technique, in which dummy convex regions
132
are formed in the trench
116
, as shown in
FIG. 12
, is proposed. By the provision of the dummy convex regions
132
, the polishing pressure is distributed over the dummy convex regions
132
. Accordingly, the concentration of the polishing pressure over the isolated effective convex region
130
is prevented, and the polishing rate at the isolated effective convex region does not become excessively greater. Consequently, the provision of the dummy convex regions
132
prevents the isolated effective convex region
130
from being excessively cut.
The technique for forming the dummy convex regions
132
is described in Japanese laid-open patent application H9-107028, Japanese laid-open patent application H9-181159, Japanese laid-open patent application H10-92921, Japanese laid-open patent application H11-26576, U.S. Pat. No. 5,885,856 and U.S. Pat. No. 5,902,752.
SUMMARY
(A) In accordance with a first embodiment of the present invention, a semiconductor device has a trench isolation region defining a row direction and first virtual linear lines extending in a direction traversing the row direction, wherein the row direction and each of the first virtual linear lines define an angle of about 2 to 40 degree. A plurality of dummy convex regions are provided in the trench isolation region, wherein the dummy convex regions are disposed on the first virtual linear lines.
The “row direction” used here refers to one direction that is virtually defined in view of an active region, a gate region, a boundary region between an n-well and a p-well and a prohibited region.
In the semiconductor device in accordance with the first embodiment, the dummy convex regions are disposed on the first virtual linear lines. In a preferred embodiment, the row direction and the first virtual linear lines define an angle of 2 to 40 degree. In other words, adjacent ones of the dummy convex regions formed on the first virtual linear lines and disposed in the row direction are mutually off set in a column direction. As a result, dummy convex regions that are mutually densely arranged can also be readily formed in an area adjacent to a prohibited area that extends in the row direction. In other words, when some of the dummy convex regions overlap the prohibited area, the other dummy convex regions are securely disposed in an area adjacent to the prohibited area. As a consequence, when the dielectric layer filled in the trench is polished, the polishing pressure is securely distributed over the dummy convex regions adjacent to the prohibited area.
Also, because the dummy convex regions are securely disposed in an area adjacent to the prohibited area, the dummy convex regions can also be securely provided in a region where a gap between adjacent dummy convex regions is narrow, in other words, where the adjacent dummy convex regions are spaced a short distance from one another.
(B) In accordance with a second embodiment of the present invention, a semiconductor device comprises a trench isolation region defining a column direction and second virtual linear lines extending in a direction traversing the column direction, wherein the column direction and each of the second virtual linear lines define an angle of 2 to 40 degree. A plurality of dummy convex regions are provided in the trench isolation region, wherein the dummy convex regions are disposed on the second virtual linear lines.
The “column direction” used here refers to one direction that is virtually defined in view of an active region, a gate region, a boundary region between an n-well and a p-well and a prohibited region.
In the semiconductor device in accordance with the second embodiment, the dummy convex regions are disposed on the second virtual linear lines. The column direction and the second virtual linear lines define an angle of about 2 to 40 degree. In other words, adjacent ones of the dummy convex regions formed on each of the second virtual linear lines and disposed in the column direction are mutually off set in the row direction. As a result, dummy convex regions that are mutually densely arranged can also be readily formed in an area adjacent to a prohibited area that extends in the column direction
Kasuya Yoshikazu
Kawahara Kei
Mori Katsumi
Brewster William M.
Chaudhuri Olik
Seiko Epson Corporation
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