Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2001-03-29
2003-09-30
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S736000, C438S780000, C438S637000
Reexamination Certificate
active
06627557
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-099760, filed Mar. 31, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
This invention relates to a method for manufacturing a semiconductor device by means of dry etching. In particular, the present invention relates to a method of forming a mask to be used for working an underlying layer, and to a method of etching by making use of the mask. This invention also relates to a semiconductor device to be formed by making use of this etching method.
Today, there is an increasing demand to further miniaturize the pattern of semiconductor elements due to an increasing integration of the semiconductor devices. Further, in view of further accelerating the response speed of the semiconductor devices, there has been tried to reduce the wiring resistance or the parasitic resistance of wiring. Meantime, the patterning of photoresist film has been performed by making use of a reflection preventive film which is formed directly below the photoresist film.
A dual damascene work is now extensively adopted in the technique of manufacturing a semiconductor device, wherein wiring grooves and contact holes associated with the wiring grooves are formed in an interlayer insulating film, and then, metallic wirings and contact plugs were buried in these grooves and holes, respectively. There are two possible alternative methods for carrying out the dual damascene work, i.e. a method wherein the contact holes are formed at first, and then, the wiring grooves are formed so as to overlap the contact holes (holes first, grooves later), and a method wherein the wiring grooves are formed at first, and then, the contact holes are formed therein (grooves first, holes later).
In the method where the wiring grooves are formed in advance in the aforementioned manufacturing method of semiconductor device, since the patterning of the contact holes are performed after the working of wiring grooves, the DOF (Depth of Focus) is caused to decrease due to the influence of the step portion of the grooves, so that as the patterning size decreases, it becomes increasingly difficult to perform a satisfactory patterning. On the other hand, in the method where the contact holes are formed in advance, since the patterning of the wiring grooves are performed after the working of contact holes, a reflection preventive film and a resist (photoresist) are caused to enter into the contact holes.
Meantime, since the resist film is required to be formed thinner in conformity with the increasing miniaturization of semiconductor device today, it is indispensable to secure a high etching selectivity between the resist film and an interlayer insulating film on the occasion of the etching work of the wiring grooves. Therefore, the reflection preventive film and the resist that have been entered into the contact holes act as a mask for the sidewalls of contact holes, thereby giving rise to the generation of residue of the interlayer insulating film on the surface of contact holes on the occasion of forming the wiring grooves. This generation of residue of the interlayer insulating film leads to a deterioration of reflow characteristics of the wiring material, and also to a cause for giving a bad influence to the electric characteristics of semiconductor device.
Further, in a situation where a portion of a semiconductor chip is subjected to a dual damascene work, and the other portion thereof is subjected to the work for forming the contact holes of high aspect ratio, since the patterning in the dual damascene work is required to be repeated at least twice, the misregistration of lithography is liable to be generated in the operation of forming the contact holes of high aspect ratio at the aforementioned other portion of the semiconductor chip. Additionally, a reflection preventive film and a resist may enter into the contact holes on the occasion of the second patterning process, thereby allowing the resist to act as a mask to make it difficult to satisfactory perform the working.
As the wirings to be formed in a semiconductor device becomes increasingly finer, the width between wirings becomes increasingly narrower. As a result, the wiring resistance is caused to increase, thereby raising the problem that the propagation velocity of signals becomes lower. As explained above, in the case of the dual damascene work, as the pattern to be formed therein becomes increasingly finer, the resist film is also required to be thinner, so that the etching is required to be performed using an interlayer insulating film having a higher etching selectivity relative to the resist film. As a result, the residue of the interlayer insulating film is caused to remain on an upper portion of contact holes on the occasion of forming the wiring grooves. This residue of the interlayer insulating film leads to a deterioration of reflow characteristics of the wiring material, and also to a cause for deteriorating the electric characteristics of semiconductor device.
In a situation where a pattern is desired to be formed on each of different kinds of film (mixed films) which have been formed in advance on the surface of a semiconductor chip, i.e. an interlayer insulating film has been formed on a portion of the surface of the semiconductor chip, while a polysilicon film has been formed on another portion of the surface of the semiconductor chip, the pattern-forming process including patterning and RIE is required to be separately performed for each kind of films, resulting in an increase in the number of steps and in deterioration of productivity.
Further, in order to make it possible to perform the fine working of a semiconductor, a reflection preventive film is formed prior to the step of forming a pattern using a resist on the occasion of working an insulating film or a metallic film. In this case, since the portion where wirings are densely located (densified portion) differs in terms of DOF (Depth of Focus) from the portion where wirings are sparsely located (sparse portion), if an isolated wiring is to be formed, the densified portion would be under-dosed, thereby rendering the wiring of this densified portion to become tapered in cross-section. On the other hand, if wirings of high-density is to be formed, the sparse portion would be over-dosed, thereby leading to the generation of skipping of pattern where the pattern in the sparse portion is failed to be formed.
BRIEF SUMMARY OF THE INVENTION
This invention has been achieved under the circumstances mentioned above, and therefore, an object of the present invention is to provide a method of manufacturing a semiconductor device, which is capable of excellently controlling the various shapes of patterns which differ depending on the region in a semiconductor chip.
Another object of the present invention is to provide a semiconductor device having precise patterns formed therein.
A still another object of the present invention is to provide a method of manufacturing a semiconductor device, which enables patterns to be worked with excellent controllability even if a film having different kinds of underlying layer is formed thereon.
Namely, the present invention is featured in that the work to form a resist mask is performed after a hard mask layer is subjected to the masking work thereof, thereby incorporating all of the hard mask into the resist; or in that the region where the resist mask exists is formed at a portion of a semiconductor chip, and the region where the hard mask exists is formed at another portion of the semiconductor chip. As a result, it becomes possible to excellently control the various shapes of patterns which differ depending on the region in a semiconductor chip, and to enable patterns to be worked with excellent controllability even if a film having different kinds of underlying layer is formed thereon.
Additional objects and advantages of the invention will be set forth in the
Matsushita Takaya
Seta Shoji
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Lee Calvin
Smith Matthew
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