Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Having substrate registration feature
Reexamination Certificate
2001-06-21
2002-09-10
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Having substrate registration feature
C257S283000, C257S797000
Reexamination Certificate
active
06448147
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing it, and in particular to a method for manufacturing a box mark for automatic overlay measurement used in a lithography process.
2. Description of the Related Art
In semiconductor device manufacture, the lithography process is required to form each of layers of a semiconductor device in a predetermined shape. In this process, it is needed when forming a resist pattern in a certain layer to conduct it while aligning a mask pattern with its underlying layer according to a predetermined standard. The predetermined standard concerning the pattern overlay accuracy is becoming strictly as the semiconductor devices become fine.
Hereafter, a box mark for automatic overlay measurement between a mask pattern and its underlying layer used in a conventional lithography process will be described.
FIGS. 1A through 1F
are sectional views for description of manufacture processes of the conventional method.
FIG. 2
is a top view for description of the conventional method. Word lines and bit lines are formed on a semiconductor substrate having devices formed thereon. Thereafter, a capacity contact pattern is formed between word lines and bit lines in a lithography process. Here, the lithography process is shown.
As shown in
FIG. 1A
, element isolation regions
102
are first formed on a semiconductor substrate
101
.
Subsequently, as shown in
FIG. 1B
, word lines
105
each having a polycide structure are formed. At this time, an integral outside box mark
105
a
for automatic misalignment measurement is also formed on a scribe line simultaneously with formation of the word lines
105
.
Subsequently, as shown in
FIG. 1C
, pad polysilicon regions
10
are formed on predetermined areas on the word lines
105
. Thereafter, an oxide film
103
having a film thickness of, for example, approximately 800 nm is deposited by using the chemical vapor deposition (CVD) method or the like. As occasion demands, reflow, silica etch back, chemical-mechanical polishing (CMP), or the like is conducted on the oxide film
103
to planarize the oxide film
103
.
As shown in
FIG. 1D
, a resist
107
is applied to the surface of the oxide film
103
. By using a mask for forming a contact hole
109
having an inside box mark
11
for automatic overlay measurement added thereto, exposure and development are conducted. Thereafter, a misalignment value from the inside box mark
11
formed over the outside box mark
105
a
is read by using an automatic overlay measuring instrument. Thereby, a misalignment value between the word line
105
and the contact hole
109
is measured.
In succession, the misalignment value is inputted as an offset value of an aligner. A resist
107
is applied on the surface of the oxide film
103
again, and exposure of the contact hole
109
is conducted.
Subsequently, as shown in
FIG. 1E
, a predetermined region of the oxide film
103
is removed, by using the photoresist
107
formed so as to have a predetermined pattern shape, as a mask, and by using anisotropic etching or the like. A contact hole
109
is thus formed. Furthermore, by way of a predetermined process, WSi is buried in the contact hole
109
, and in addition, WSi serving as a bit line
111
is deposited.
Thereafter, in the same way as the word line
105
, exposure and development are conducted by using a mask for forming the bit lines
111
having an integral outside box mark
111
a
for automatic overlay measurement added thereto. The bit lines
111
are thus formed, and the outside box mark
111
a
is newly formed. At this time, misalignment of the bit lines
111
is measured by using the box mark
111
a
formed at the time of contact described before.
Subsequently, as shown in
FIG. 1F
, an oxide film
150
having a film thickness of, for example, approximately 800 nm is deposited by using the chemical vapor deposition (CVD) method or the like. As occasion demands, reflow, silica etch back, chemical-mechanical polishing (CMP), or the like is conducted on the oxide film
150
to planarize the oxide film
150
.
Thereafter, a photoresist film
113
is applied to the surface of the oxide film
150
. By using a mask for forming capacity contacts
114
having an inside box mark
17
for automatic overlay measurement added thereto, exposure and development are conducted. Thereafter, by using the automatic overlay measuring instrument, a misalignment value in the X direction (the lateral direction of
FIGS. 1A through 1F
) is read from the outside box mark
105
a
formed in the process of
FIG. 1B
, and a misalignment value in the Y direction (the depth direction of
FIGS. 1A through 1F
) is read from the outside box mark
111
a
formed in the process of FIG.
1
E. Between wiring lines forming the shape of #, the capacity contacts
114
are thus formed.
In the above described integral outside box mark for automatic overlay measurement, however, two box marks are required to measure the misalignment values in the X direction (word line) and Y direction (bit line) when forming capacity contacts between word lines and between bit lines. Therefore, there is a problem that it takes a time to measure the misalignment values and analyze the measurement results.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a method for shortening, in the manufacture processes of a semiconductor device, the time for measuring the overlay between the underlying layer and a mask pattern at the time of lithography, and the time for analyzing the measurement result.
A semiconductor device according to the present invention has such patterns of a plurality of layers formed on a substrate that respective layers are laminated in predetermined position relations. In the present invention, a first mark disposed at the time of first pattern formation and a second mark disposed at the time of second pattern formation form one misalignment measurement mark, and position aligning for third or subsequent pattern formation is conducted with the misalignment measurement mark.
In accordance with another aspect of the present invention, a semiconductor device includes: a first mark forming a part of a misalignment measurement mark disposed in a predetermined position of a substrate at the time of first pattern formation; and a second mark forming another part of said misalignment measurement mark disposed at the time of second pattern formation, wherein the first mark and the second mark form one of the misalignment measurement mark, and the misalignment measurement mark is used for position aligning with a mark of mask side at the time of third or subsequent pattern formation.
A manufacture method according to the present invention, said semiconductor device having such patterns of a plurality of layers formed on a substrate that respective layers are laminated in predetermined position relations, includes the steps of: forming a first mark in a predetermined position of the substrate at the time of first pattern formation, the first mark forming a part of a misalignment measurement mark used in a subsequent pattern forming step; forming a second mark forming another part of said misalignment measurement mark at the time of second pattern formation; and positioning and adjusting a mark of mask side at the time of third or subsequent pattern formation by using the misalignment measurement mark produced in previous pattern forming process, and conducting third pattern formation or subsequent pattern formation.
In accordance with a method for manufacturing a semiconductor device according to the present invention, a # shape is formed by laying two vertical lines formed by word lines over two parallel lines formed of bit lines, as an outside box mark for automatic overlay measurement formed on a semiconductor substrate. Thereby, a misalignment value from the word line and a misalignment value from the bit line can be measured by using one box mark. As a result, it becomes also possible to shorten
Blum David S.
Bowers Charles
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