Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2001-03-19
2002-07-16
Graybill, David E. (Department: 2827)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S119000
Reexamination Certificate
active
06420210
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a semiconductor device and method for manufacturing the same, more particularly to a semiconductor device that can be produced at a relatively low manufacturing cost and with a relatively high production yield.
2. Description of the Related Art
Referring to
FIGS. 1 and 2
, a conventional semiconductor device
1
is shown to comprise a semiconductor chip
10
, a dielectric tape layer
2
and a printed circuit board
3
.
The semiconductor chip
10
has a pad mounting surface
12
with a plurality of bonding pads
11
provided thereon. The dielectric tape layer
2
has an adhesive surface
21
adhered onto the pad mounting surface
12
of the semiconductor chip
10
, and a plurality of holes
20
that are registered with the bonding pads
11
to expose the latter. The dielectric tape layer
2
further has a wire mounting surface
22
opposite to the adhesive surface
21
. A plurality of wires
23
that traverse the holes
20
are disposed on the wire mounting surface
22
. A wire-bonding machine (not shown) processes the portions of the wires
23
that traverse the holes
20
(in the direction of the arrows shown in
FIG. 1
) so as to bond the wires
23
to the bonding pads
11
in the holes
20
. Solder balls
24
are subsequently formed on the wires
23
. The printed circuit board
3
has a circuit layout surface
30
formed with circuit traces
31
that bond with the solder balls
24
to establish electrical connection between the circuit traces
31
and the bonding pads
11
via the solder balls
24
and the wires
23
.
Some of the drawbacks of the conventional semiconductor device
1
are as follows:
1. An expensive wire-bonding machine is needed to establish connection between the wires
23
and the bonding pads
11
, thereby increasing the production costs. Also, defective products are produced during the wire-bonding operation due to inadequacies of the latter. Particularly, defective products are formed when wires break during the wire-bonding operation, thereby reducing the production yield.
2. The wires
23
are susceptible to oxidation and corrosion because they are exposed to air, thereby affecting reliability of the semiconductor device
1
.
3. Solder balls
24
are needed to establish connection between the circuit traces
31
on the printed circuit board
3
and the semiconductor chip
10
. The solder balls
24
are liable to drop off or form unstable electrical contacts, thereby affecting adversely the production yield.
4. Because solder balls
24
are used to connect the printed circuit board
3
and the semiconductor chip
10
, the contact area between the printed circuit board
3
and the semiconductor chip
10
is relatively small and can lead to eventual undesired separation between the printed circuit board
3
and the semiconductor chip
10
.
SUMMARY OF THE INVENTION
Therefore, the main object of the present invention is to provide a semiconductor device and a method for manufacturing a semiconductor device capable of overcoming the aforesaid drawbacks that are associated with the prior art.
According to one aspect of the present invention, a semiconductor device comprises:
a semiconductor chip having a pad mounting surface with a plurality of bonding pads provided thereon;
a dielectric tape layer having opposite first and second adhesive surfaces, the first adhesive surface being adhered onto the pad mounting surface of the semiconductor chip, the dielectric tape layer being formed with a plurality of holes at positions registered with the bonding pads to expose the bonding pads, each of the holes being confined by a wall that cooperates with a registered one of the bonding pads to form a contact receiving space;
a plurality of conductive contacts placed in the contact receiving spaces, respectively; and
a printed circuit board having a circuit layout surface adhered onto the second adhesive surface of the dielectric tape layer, the circuit layout surface being formed with circuit traces that are bonded to the conductive contacts to establish electrical connection with the bonding pads.
According to another aspect of the present invention, a method for manufacturing a semiconductor device comprises:
adhering a first adhesive surface of a dielectric tape layer onto a pad mounting surface of a semiconductor chip, the dielectric tape layer being formed with a plurality of holes at positions registered with bonding pads provided on the pad mounting surface to expose the bonding pads, each of the holes being confined by a wall that cooperates with a registered one of the bonding pads to form a contact receiving space;
placing a plurality of conductive contacts in the contact receiving spaces, respectively; and
adhering a circuit layout surface of a printed circuit board onto a second adhesive surface of the dielectric tape layer opposite to the first adhesive surface, and bonding circuit traces formed on the circuit layout surface to the conductive contacts to establish electrical connection with the bonding pads.
Preferably, the second adhesive surface is provided with a heat-curable adhesive having a curing point that is lower than melting point of the conductive contacts. Thus, adhering of the printed circuit board onto the dielectric tape layer and bonding of the circuit traces to the conductive contacts can be performed simultaneously via a heat curing operation such that the circuit layout surface is already adhered onto the second adhesive layer prior to melting of the conductive contacts.
REFERENCES:
patent: 5394303 (1995-02-01), Yamaji
patent: 5468681 (1995-11-01), Pasch
patent: 5776799 (1998-07-01), Song et al.
patent: 0329317 (1989-08-01), None
patent: 0740340 (1996-10-01), None
patent: 58035935 (1983-03-01), None
patent: 2058793 (1990-10-01), None
patent: 4199723 (1992-07-01), None
patent: 5347328 (1993-12-01), None
patent: 7240434 (1995-09-01), None
patent: 8148494 (1996-06-01), None
patent: 9205582 (1992-04-01), None
patent: 9857370 (1998-12-01), None
Patent Abstracts of Japan JP 04199723 dated Jul. 20, 1992.
English Abstract of WO 98/57370 Dated Dec. 17,1998.
Burdick, B. et al. “Extension of The Chip-On-Flex Technology to Known Good Die.” International Journal of Microcircuits and Electronic Packaging Society, vol. 19, No. 4, (1996) pp. 435-440.
English Abstract of JP 5347328 Dated Dec. 27, 1993.
English Abstract of Equivalent JP 2058793 Patent of JP 58035935 Dated Mar. 2, 1983.
English Abstract of JP 8148494 Date Jun. 7, 1996.
English Abstract of JP 7240434 Dated Sep. 12, 1995.
Computech International Ventures Limited
Graybill David E.
Ladas & Parry
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