Semiconductor device and method for manufacturing the same

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration

Reexamination Certificate

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Details

C257S698000, C257S773000, C257S775000, C257SE21577, C257SE21578

Reexamination Certificate

active

08004090

ABSTRACT:
A first insulating layer including a first contact pad made of conductive polysilicon and a second insulating layer including a second contact pad are formed over a semiconductor silicon layer. After this, a via hole for a through-hole electrode is formed until the via hole penetrates through at least the semiconductor silicon layer and the first contact pad and reaches to the second contact pad.

REFERENCES:
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patent: 2007/0262424 (2007-11-01), Hiatt
patent: 2007/0262464 (2007-11-01), Watkins et al.
patent: 2007/0284729 (2007-12-01), Kwon et al.
patent: 2007/0287265 (2007-12-01), Hatano et al.
patent: 2008/0136038 (2008-06-01), Savastiouk et al.
patent: 2008/0237849 (2008-10-01), Pratt
patent: 2009/0045502 (2009-02-01), Adkisson et al.
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patent: 2005-093486 (2005-04-01), None
patent: 2006-032695 (2006-02-01), None
patent: 2006-108520 (2006-04-01), None
patent: 2006-261403 (2006-09-01), None
P.S. Andry et al., A CMOS-compatible Process for Fabricating Electrical Through-vias in Silicon, 2006 Electronic Components and Technology Conference, pp. 1-7.

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