Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Making plural separate devices
Reexamination Certificate
2003-03-10
2004-03-02
Picardat, Kevin M. (Department: 2822)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Making plural separate devices
C438S459000, C438S460000, C438S464000
Reexamination Certificate
active
06699735
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and method for manufacturing the semiconductor device, and particularly to a package for the semiconductor device.
2. Description of the Related Art
High density mounting of semiconductor devices has been advancing in recent years, and the main focus has been on semiconductor devices such as chip size packages.
As an example of a chip size package structure semiconductor device, Japanese Patent Application Non. Hei 11-102599 discloses a semiconductor device having a semiconductor element thickness of less than 200 &mgr;m and a large ratio of resin compared to the semiconductor elements, in order to solve a problem where cracks arise at a joining section between the semiconductor device and a mounting substrate due to differences in the thermal expansion coefficients of the semiconductor elements and the mounting substrate.
Also, Japanese Patent laid open No. Hei. 8-64725 discloses a chip size package where sealing resin is formed on a circuit formation surface of a semiconductor element and a surface opposite the circuit formation surface, and warping of the wafer is prevented.
In a semiconductor device having the most recent chip size package structure as described above, in order to stop cracking at a junction section between the semiconductor element and the mounting substrate, the trend has been to make the thickness of the semiconductor element thin, and make a proportion of resin large compared to the semiconductor element.
However, if the thickness of the semiconductor element is made less than 200 &mgr;m and the ratio of the thickness of the semiconductor element to the thickness of the resin becomes small, in the case where resin is only formed on the circuit formation surface side of the semiconductor element, warping of the wafer occurs even for individual semiconductor elements obtained by dividing the wafer.
In the semiconductor device of Japanese Patent Laid-open No. Hei. 8-64725. There is also a problem of damage to the wafer at the time of conveying, when the thickness of the wafer is less than 200 &mgr;m, if resin sealing is carried out after grinding the rear surface of the semiconductor wafer.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a chip size package structure semiconductor device having semiconductor elements of less than 200 &mgr;m in thickness, which can be favorably mounted in a mounted substrate.
Another object of the present invention is to provide a manufacturing method for a chip size package structure semiconductor device that has sealing resin formed on both surfaces of a semiconductor element, and particularly a method of manufacturing a thin semiconductor device in which the semiconductor element has a thickness of less than 200 &mgr;m.
In order to achieve the above described objects, a semiconductor device of the present invention comprises a semiconductor element with a thickness of less than 200 &mgr;m, a protruding electrode formed on a circuit formation surface of the semiconductor element, sealing resin, for sealing the circuit formation surface and the protruding electrode to cause an upper surface of the protruding electrode to be exposed, and sealing resin for sealing a surface of the semiconductor element opposite to the circuit formation surface, where if the thickness of the sealing resin for sealing the circuit formation surface of the semiconductor element is designated A and the thickness of the sealing resin for sealing the surface of the semiconductor element opposite to the circuit formation surface is designated B, the expression 0.2≦A/B≦1, or 0.2≦B/A≦1 is satisfied.
Various modifications are possible to the present invention, and will be understood by one skilled in the art with reference to the claims and embodiments contained herein.
REFERENCES:
patent: 5554887 (1996-10-01), Sawai et al.
patent: 5757066 (1998-05-01), Inoue et al.
patent: 5986335 (1999-11-01), Amagai
patent: 6093958 (2000-07-01), Inaba
patent: 6562658 (2003-05-01), Ohcuhi et al.
patent: 2002/0050624 (2002-05-01), Vandeputte et al.
patent: 08064725 (1996-03-01), None
patent: 08064725 (1996-03-01), None
patent: 11-054564 (1999-02-01), None
patent: 11-121525 (1999-04-01), None
Ohuchi Shinji
Tanaka Yasuo
Oki Electric Industry Co. Ltd.
Picardat Kevin M.
Rabin & Berdo P.C.
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