Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2000-09-21
2003-02-11
Fahmy, Wael (Department: 2823)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S118000, C438S127000
Reexamination Certificate
active
06518093
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same, more in particular to the semiconductor device implementing the smaller package size and the method for manufacturing the same.
(b) Description of the Related Art
New packages for a semiconductor device have been developed one after another for responding to the demands of a higher degree of performance, miniaturization or operational speed. The planar miniaturization and the thinner structure of the semiconductor device are realized by higher integration of mounting semiconductor chips (sometimes referred to as “LSI chip”), thereby intending the still higher degree of the performance and the operational speed of an electronic device. In order to realize the higher degree of the performance of the LSI chips, a flip chip ball grid array (FCBGA) process has been developed.
A conventional semiconductor device including a package structure formed by the FCBGA process shown in
FIG. 1
includes an LSI chip
11
having an interconnect pattern, a plurality of solder bumps
12
corresponding to the interconnect pattern, and a multi-layered interposer
24
having a plurality of electrode pads
33
. The interposer has roles of elevating the handling performance of the semiconductor device, obtaining an arrangement of solder balls
25
corresponding to connection parts of a standardized substrate, and further protecting the surface of the LSI chip
11
from a probe during the performance test of the LSI chip
11
.
A solder resist
34
is formed on the surface of the interposer
24
except for the electrode pads
33
, and the solder balls are formed on the surface reverse to the electrode pads
34
. Underfill resin
14
is filled in a gap among the LSI chip
11
, the solder bumps
12
and the electrode pad
33
and cured while the solder bumps
12
and the electrodes pads
33
are electrically and mechanically connected.
For the manufacture of the conventional semiconductor device, at first the LSI chip
11
is aligned with the interposer
24
, and the chip
11
and the interposer
24
are bonded to each other by means of re-flowing. After the washing depending on the necessity, the underfill resin
14
is further filled in the gap among the LSI chip
11
, the solder bumps
12
and the electrode pad
33
and cured. Then, connection terminals such as the solder balls
25
are mounted on the reverse surface of the interposer
24
depending on the necessity.
The difficulty of peeling off the LSI chip
11
from the interposer
24
in the conventional semiconductor device forces the LSI chip judged to be inferior in the performance test to be scraped with the interposer
24
. Accordingly, the interposer
24
must be manufactured at a cost as low as possible, and is manufactured by using an aligner without using an LSI stepper. Although the cost-down can be attained in the manufacturing method, the miniaturization becomes more difficult than the case where the LSI stepper is employed, thereby making the package itself large-scaled as well as the interposer
24
compared with the LSI chip
11
.
A bare chip process may be used for miniaturization and/or simplification of the package. However, the LSI chip formed by the process is entirely thin and includes no protection layer, and the handling must be carefully conducted with burdensome operations. Further, the semiconductor devices manufactured by the bare chip process are likely subjected to damages such as a probing injury or scar generated during the test of the electrode pad. Accordingly, the performance test can not be easily conducted.
SUMMARY OF THE INVENTION
In view of the foregoing, an object of the present invention is to provide a semiconductor device in which a package is miniaturized without using an interposer and to which the handling and the performance test are easily conducted while realizing the cost down.
The present invention provides, in a first aspect thereof, a method for manufacturing a semiconductor device including the steps of: forming a plurality of metallic connection members on at least one of a temporary substrate and a semiconductor chip; thrusting the temporary substrate and the semiconductor chip against each other to press the metallic connection members therebetween; filling a space between the temporary substrate and the semiconductor chip with resin to embed therein the metallic connection members; curing the resin to form a first protective layer; and removing the temporary substrate from the first protective layer and the metallic connection members.
The present invention provides, in a second aspect thereof, a semiconductor device including: a semiconductor chip having thereon a plurality of chip electrodes, a plurality of metallic connection members in electric contact with the respective chip electrodes, a resin protective layer filling a space between the metallic connection members, said resin protective layer having a top surface exposing a top surface of each of the metallic connection members.
In accordance with the first and the second aspect of the present invention, the package of the semiconductor device can be miniaturized with the realization of the cost down by using no interposer, and the handling and the performance test are more conveniently conducted.
The above and other objects, features and advantages of the present invention will be more apparent from the following description.
REFERENCES:
patent: 5912505 (1999-06-01), Itoh et al.
patent: 6040630 (2000-03-01), Panchou et al.
patent: 6100597 (2000-08-01), Nakamura
patent: 6103551 (2000-08-01), Ono et al.
patent: 6117759 (2000-09-01), Greer et al.
patent: 6132646 (2000-10-01), Zhou et al.
patent: 6189208 (2001-02-01), Estes et al.
patent: 6229220 (2001-05-01), Saitoh et al.
patent: 6245595 (2001-06-01), Nguyen et al.
patent: 6348399 (2002-02-01), Lin
Fahmy Wael
Hayes & Soloway PC
Kebede Brook
NEC Corporation
LandOfFree
Semiconductor device and method for manufacturing same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device and method for manufacturing same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and method for manufacturing same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3177795