Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2002-10-25
2004-09-14
Clark, S. V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S532000, C438S248000
Reexamination Certificate
active
06791156
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATION
This application is based upon and claims the benefit of Japanese Patent Application No. 2001-329449 filed on Oct. 26, 2001, the contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to an MOS semiconductor device in a complex semiconductor device using a silicon-on-insulator (SOI) substrate and a method for manufacturing it. More particularly, the present invention relates to a semiconductor device that offers improved characteristics in an insulating layer between electrodes in an MOS capacitor and a method of manufacturing it.
In recent years, SOI substrates have come to be widely used for semiconductor devices that include a multitude of devices of several different types on a semiconductor substrate. Because an area that includes the semiconductor devices and the semiconductor substrate are separated by an oxide film, which is a buried insulating film, in a semiconductor device having an SOI structure manufactured using an SOI substrate, an SOI semiconductor device offers superior electrical characteristics. It has been reported on many occasions, however, that a quality of an insulating film in an MOS semiconductor device formed on an SOI substrate is inferior to an insulating film formed on a regular silicon substrate.
An MOS capacitor
1
, having a cross-sectional structure shown in
FIG. 14
, is an example of an MOS capacitor formed on an SOI substrate. The MOS capacitor
1
includes a support substrate
2
, an oxide film
3
on the support substrate
2
, and a silicon layer
4
on the oxide film
3
. On a surface of the silicon layer
4
on an SOI substrate
5
are a diffusion layer
6
, which functions as one of a pair of capacitor electrodes; LOCOS
7
; and a capacitor thermal oxide film
8
which functions as a capacitor insulating film. A capacitor upper electrode
9
, which functions as the other capacitor electrode, is on top of the capacitor thermal oxide film
8
.
As shown in
FIG. 15
, compared with MOS capacitors formed using silicon substrates with an identical manufacturing method, MOS capacitors on the SOI substrates
5
show a higher rate of mode B failures, which are infant mortality failures caused by the capacitor thermal oxide film
8
breaking down at a lower voltage level than a true breakdown voltage.
The causes for a high rate of mode B failures for the MOS capacitors
1
on the SOI substrates
5
will be described next.
On the SOI substrate
5
, the oxide film
3
, having a different coefficient of thermal expansion than the silicon substrate
2
, is on the silicon substrate
2
, and the silicon semiconductor layer
4
is on the oxide film
3
. When the SOI substrate
5
goes through a thermal treatment in a process of manufacturing the MOS capacitor
1
, the quality of the capacitor thermal oxide film
8
is adversely affected, and a bimetal effect, characteristic to the SOI substrate
5
, is created.
Because of the bimetal effect in the SOI substrate
5
, the diffusion layer
6
and the capacitor thermal oxide film
8
on the diffusion layer
6
seem to behave differently from corresponding parts would on a regular silicon substrate.
Another example of a capacitor insulating film that may be used for an MOS capacitor on a silicon substrate is an oxide nitride oxide (ONO) film, which is a multilayer film that includes silicon oxide films and a silicon nitride film. The ONO film includes three layers of a silicon oxide film, a silicon nitride film, and another silicon oxide film, and the silicon nitride film is sandwiched between the two silicon oxide films.
As shown in
FIG. 16
, the rate of mode B failures goes down, when an ONO film is used, instead of the capacitor thermal oxide film
8
, in the MOS capacitor, compared with the failure rate shown in FIG.
14
. However, as shown in
FIG. 17
, there is a high rate of time-dependent random failures.
FIG. 17
shows failure rates over time of device operation, measured using a constant voltage time-dependent dielectric breakdown (TDDB) method. For this reason, the yields of the SOI semiconductor devices, having the MOS capacitor
1
on the SOI substrate
5
, cannot be improve simply by using the ONO film for the capacitor insulating film in the MOS capacitor
1
formed on the SOI substrate
5
.
SUMMARY OF THE INVENTION
The present invention addresses the issue described above by, firstly, reducing the rates of mode B failures, believed to be caused by the bimetal effect in an SOI substrate resulting from a thermal treatment of an MOS device formed on the SOI substrate. Secondly, the present invention lengthens the relative time to TDDB failures, while reducing the rates of mode B failures by improving the dielectric breakdown voltage, in the MOS devices formed on the SOI substrates in SOI semiconductor devices.
The SOI semiconductor device that achieves the first objective includes an SOI substrate, an MOS capacitor, and a trench isolation layer. The SOI substrate includes a supporting substrate, a buried oxide film, and a silicon semiconductor layer. The MOS capacitor includes a buried layer that functions as one of the capacitor electrodes and is located in the silicon semiconductor layer; a capacitor insulating layer on top of the buried layer; and an upper layer electrode that functions as the other capacitor electrode and is located on top of the capacitor insulating film. The trench isolation layer surrounds the MOS capacitor in order to insulate and isolate the MOS capacitor. The trench isolation layer has a coefficient of thermal expansion that is different from the silicon semiconductor layer.
The trench isolation layer alleviates the bimetal effect that is characteristic to the SOI substrate. For this reason, the trench isolation layer effectively prevents film quality from degrading in the gate insulating film, especially in the MOS capacitor for buffering against surges, which would be large in both capacitance and size.
By the way, each MOS capacitor should preferably be isolated individually by a trench isolation layer in an SOI semiconductor device structure that includes a multitude of MOS capacitors. If the capacitors are small in capacitance and size, however, the multitude of MOS capacitors may be placed in a single isolated area surrounded by a single trench isolation layer.
An SOI semiconductor device that achieves the second objective includes an SOI substrate, which includes a supporting substrate, a buried oxide film, and a silicon semiconductor layer; and an MOS capacitor, which includes a buried layer located in the silicon semiconductor layer and functions as one of the capacitor electrodes; a capacitor insulating layer on the buried layer; and an upper layer electrode which is on top of the capacitor insulating layer and functions as the other capacitor electrode. The capacitor insulating film in the MOS capacitor is an ONO film, which includes a lower layer oxide film in contact with the buried layer; a silicon nitride film on the lower layer oxide film; and an upper layer oxide film on top of the silicon nitride film. The lower layer oxide film is less than or equal to 50 nm in thickness.
By making the lower layer oxide film, which tends to be affected by surface defects on the semiconductor surface, thin in the ONO film, a capacitor insulating film that offers a relatively higher breakdown voltage and longer mean time to TDDB failure may be formed on the SOI substrate.
As long as the film thickness of the lower layer oxide film in the ONO film is less than or equal to 50 nm and greater than or equal to 25 nm, capacitance of the MOS capacitor that uses the ONO film would be uniform and show stable characteristics. If the lower layer oxide film in the ONO film were extremely thin, capacitance of the MOS capacitor would become non-uniform due to conditions at the silicon/oxide film interface.
When the silicon nitride film in the ONO film is greater than or equal to 40 nm in thickness, the resulting capacitor insulating film would offer an even higher breakdown voltage
Clark S. V.
Denso Corporation
Posz & Bethards, PLC
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